GS820E32 데이터 시트보기 (PDF) - Giga Semiconductor
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GS820E32 Datasheet PDF : 23 Pages
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GS820E32T/Q-150/138/133/117/100/66
AC Test Conditions
Parameter
Conditions
Input high level
Input low level
Input slew rate
Input reference level
Output reference level
Output load
2.3V
0.2V
1V/ns
1.25V
1.25V
Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ.
4. Device is deselected as defined by the Truth Table.
Output Load 1
DQ
Output Load 2
2.5V
50Ω
30pF*
DQ
225Ω
VT=1.25V
* Distributed Test Jig Capacitance
5pF* 225Ω
DC Electrical Characteristics
Parameter
Input Leakage Current
(except mode pins)
ZZ Input Current
Mode Pin Input Current
Output Leakage Current
Output High Voltage
Output High Voltage
Output Low Voltage
Symbol Test Conditions
IIL
VIN = 0 to VDD
IINZZ
VDD ≥ VIN ≥ VIH
0V ≤ VIN ≤ VIH
IINM
VDD ≥ VIN ≥ VIL
0V ≤ VIN ≤ VIL
IOL
Output Disable,
VOUT = 0 to VDD
VOH IOH = - 4mA, VDDQ=2.375V
VOH IOH = - 4mA, VDDQ=3.135V
VOL
IOL = 4mA
Min
-1uA
-1uA
-1uA
-300uA
-1uA
-1uA
1.7V
2.4V
Max
1uA
1uA
300uA
1uA
1uA
1uA
0.4V
Rev: 1.03 2/2000
11/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.
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