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HSP50216

Four-Channel Programmable Digital Downconverter

Intersil 

HSP50216

Input Select/Format Block

TEST ENI

SELECT

(IWA *000 - 12

or GWA F804 - 12)

EXTERNAL/TEST

SELECT

(IWA *000 - 15

or GWA F804 - 15)

μP TEST

REGISTER

(GWA F807 - 15:0)

TESTENBIT

(IWA *000 - 11

or GWA F804 - 11)

TESTENSTRB

(GWA F808)

A(15:0)

ENIA

B(15:0)

ENIB

15:0

TESTEN

15:0

OFFSET BINARY

OR

TWO’s COMPLEMENT

(IWA *000 - 10

or GWA F804 - 10)

11/3, 12/3,

13/3, 14/2

(IWA *000 - 8:7

or GWA F804 - 8:7)

FIXED POINT

OR

FLOATING POINT

(IWA *000 - 9

or GWA F804 - 9)

15:0

FLOATING POINT

FORMAT

TO

R

FIXED POINT

E

G

EN

PROGRAMMABLE

DELAY

15:0

DATA

TO

NCO/MIXER

OR

LEVEL

DETECTOR

C(15:0)

ENI

ENIC

D(15:0)

ENID

NOTE: ENI* SIGNALS

ARE ACTIVE HIGH

(INVERTED AT THE I/O PAD)

EXTERNAL DATA

INPUT SELECT

(IWA *000 - 14:13

or

GWA F804 - 14:13)

INPUT ENABLE HOLD OFF

(ENABLED BY SYNCI)

(GWA F802 - 30)

DE-MULTIPLEX

CONTROL (0-7)

(IWA *000 - 6:4

or GWA F8O4 - 6:4)

INTERPOLATED/GATED

MODE

(IWA *000 - 3

or GWA F804 - 3)

DATA

SAMPLE

ENABLE

CARRIER OFFSET

FREQUENCY (COF)

PN

ENABLE PN

(IWA *000 - 0)

PN TO

CARRIER

NCO/MIXER

COF TO

CARRIER

NCO/MIXER

RESAMPLER

OFFSET FREQUENCY

(SOF)

SOF TO

RESAMPLER

NCO

COF SYNC

ENABLE

COF

(1WA *000 - 2)

COF SYNC TO

CARRIER

NCO/MIXER

SOF SYNC

ENABLE

SOF

(IWA *000 - 1)

SOF SYNC TO

RESAMPLER

NCO

Each front end block and the level detector block contains an

input select/format block. A functional block diagram is

provided in the above figure. The input source can be any of

the four parallel input busses (See Microprocessor Interface

section, Table 3, “CHANNEL INPUT SELECT/FORMAT

REGISTER (IWA = *000h),” on page 32 or a test register

loaded via the processor bus (see Microprocessor Interface

section, Table 42, “mP/TEST INPUT BUS REGISTER (GWA

= F807h),” on page 45).

The input to the part can operate in a gated or interpolated

mode. Each input channel has an input enable (ENIx, x = A,

B, C or D). In the gated mode, one input sample is

processed per clock that the ENIx signal is asserted (low).

Processing is disabled when ENIx is high. The ENIx signal is

pipelined through the part to minimize delay (latency). In the

interpolated mode, the input is zeroed when the ENIx signal

is high, but processing inside the part continues. This mode

inserts zeros between the data samples, interpolating the

input data stream up to the clock rate. On reset, the part is

set to gated mode and the input enables are disabled. The

inputs are enabled by the first SYNCI signal.

The input section can select one channel from a multiplexed

data stream of up to 8 channels. The input enable is delayed

by 0 to 7 clock cycles to enable a selection register. The

register following the selection register is enabled by the

non-delayed input enable to realign the processing of the

channels. The one-clock-wide input enable must align with

the data for the first channel. The desired channel is then

selected by programming the delay. A delay of zero selects

the first channel, a delay of 1 selects the second, etc.

7

FN4557.6

August 17, 2007

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