FS6128-04 데이터 시트보기 (PDF) - ON Semiconductor
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FS6128-04 Datasheet PDF : 6 Pages
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FS6128-04
Table 5: DC Electrical Specifications
Parameter
Symbol
Conditions/Descriptions
Min. Typ. Max.
Units
Overall
Supply current, dynamic, with loaded outputs IDD
fXAL = 13.5MHz; CL = 10pF; VDD = 3.6V
30
mA
Supply current, static
IDD
XIN = 0V; VDD = 3.6V
3
mA
Voltage-Controlled Crystal Oscillator (contact factory for approved crystal sources or other application assistance)
Crystal loading capacitance at center tuning
voltage
CL(xtal)
Order crystal for this capacitance
(parallel load) at desired center
frequency
14
pF
Crystal resonator motional capacitance
C1
Specified motional capacitance of the
crystal will affect pullability (see text)
25
fF
XTUNE effective range
0
3
V
Synthesized load capacitance min.
CL1
@V(XTUNE) = minimum value
10
pF
Synthesized load capacitance max.
CL2
@V(XTUNE) = maximum value
20
pF
VCXO tuning range
fXTAL = 13.5MHz; CL(xtal) = 14pF; C1(xtal)
= 25fF (peak-to-peak)
300
ppm
VCXO tuning characteristic
Note: positive change of XTUNE =
positive change of VCXO frequency
150
ppm/V
Crystal drive level
RXTAL = 20Ω; CL = 20pF
200
μW
Clock Output (CLK)
High-level output source current*
IOH
VO = 2.0V
-40
mA
Low-level output sink current*
IOL
VO = 0.4V
17
mA
Output impedance*
ZOH
VO = 0.1VDD; output driving high
ZOL
VO = 0.1VDD; output driving low
25
25
Ω
Short circuit source current*
IOSH
VO = 0V; shorted for 30s, max.
-55
mA
Short circuit sink current*
IOSL
VO = 3.3V; shorted for 30s, max.
55
mA
Note: Unless otherwise stated VDD = 3.3V ±10% no load on any output and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an
asterisk (*) represent nominal characterization data and are not production tested to any specific limits. Where given, MIN and MAX characterization
data are ±3σ from typical. Negative currents indicate current flows out of the device.
Table 6: AC Timing Specifications
Parameter
Symbol Conditions/Descriptions
Min. Typ. Max. Units
Overall
VCXO stabilization time*
tVCXOSTB
From power valid
10
ms
PLL stabilization time*
tPLLSTB
From VCXO stable
100
μs
Synthesis error
(Unless otherwise noted in frequency table)
0
ppm
Clock Output (CLK)
Duty cycle*
Ratio of high pulse width (as measured from rising edge to next
falling edge at VDD/2) to one clock period
45
55
%
Jitter, period (peak-peak)* tj(ΔP)
From rising edge to next rising edge at VDD/2, CL = 10pF 200 ps
200
ps
Jitter, long term (σγ(τ)
tj(LT)
From 0-500μs at VDD/2, CL = 10pF compared to ideal clock source
100
ps
Rise time*
tr
VDD = 3.3V; VO = 0.3V to 3.0V; CL = 10pF
1.7
ns
Fall time*
tf
VDD = 3.3V; VO = 3.0V to 0.3V; CL = 10pF
1.7
ns
Note: Unless otherwise stated, VDD = 3.3V ±10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an
asterisk (*) represent nominal characterization data and are not production tested to any specific limits. Where given, MIN and MAX characterization
data are ±3σ from typical.
Rev. 2 | Page 4 of 6 | www.onsemi.com
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