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EUP2561JIR0 데이터 시트보기 (PDF) - Eutech Microelectronics Inc

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EUP2561JIR0
EUTECH
Eutech Microelectronics Inc EUTECH
EUP2561JIR0 Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
PC Board Layout
Due to fast switching waveforms and high-current
paths, careful PC board layout is required. An evalua-
tion kit is available to speed design.
When laying out a board, minimize trace lengths
between the IC and RSENSE, the inductor, the diode, the
input capacitor, and the output capacitor. Keep traces
short, direct, and wide. Keep noisy traces, such as the
LX node trace, away from CS. The IN bypass
capacitor (CIN) should be placed as close to the IC as
possible. PGND and GND should be connected
directly to the exposed paddle underneath the IC. The
ground connections of CIN and COUT should be as close
together as possible. The traces from IN to the inductor
and from the Schottky diode to the LEDs may be
longer.
EUP2561
DS2561 Ver1.0 Dec. 2006
8

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