CS1112 데이터 시트보기 (PDF) - ON Semiconductor

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CS1112

Quad Power Output Driver

ON Semiconductor 

CSB (Setup)

CSB

CS1112

SERIAL PERIPHERAL INTERFACE TIMING REQUIREMENTS

SI (Setup)

CSB (Hold)

SCLK

SI

SO

1

MSB

2

SI (Hold)

3

Xfer Delay

MSB

70% VDD

30% VDD

SO(Delay)

SO(Rise,Fall)

Figure 1.

CSB

OUTX

tf

tphl

tr

tplh

Figure 2.

BLOCK DIAGRAM

VPWR

CSB

SI

SCLK

SO

VDD

ROSC

IN0 IN1 IN2 IN3

VDD

10 µA

Overvoltage/

Undervoltage

Lockout

10 µA

Serial

Peripheral

Interface

Data 0

Data 1 to 3

Fault 1 to 3

VREG

Gate

Drive

ILIMIT

+

– RS

10 µA OUT0

OUT1

OUT2

OUT3

Serial D/O

Line Driver

Power On

Reset

Bias

RESET

OUT

RESET

ENABLE

4.0 ms

Fault Timer

Fault 0

Open Load

Data 0

–

+

1/2 VDD

Data 0

Shorted Load

GND

STATUS

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