CDB4215 데이터 시트보기 (PDF) - Cirrus Logic
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CDB4215 Datasheet PDF : 52 Pages
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CS4215
Control Time Slot 3, Serial Port Control Register
Register
Reset (R)
D7 D6 D5 D4 D3 D2 D1 D0
ITS MCK2 MCK1 MCK0 BSEL1 BSEL0 XCLK XEN
0
0
0
0
1
0
0
1
BIT
XEN
XCLK
NAME
Transmitter Enable
Transmit Clock
BSEL1-0 Select Bit Rate
MCK2-0 Clock Source Select
ITS
Immediate Three-
State
VALUE
0
1
0
1
00
0
01
1
10
2
11
3
000 0
001 1
010 2
011 3
100 4
0
1
FUNCTION
Enable the serial data output.
R Disable (high-impedance state) serial data output.
R Receive SCLK and FSYNC from external source
SLAVE Mode
Generate SCLK and FSYNC
MASTER Mode
64 bits per frame.
128 bits per frame.
R 256 bits per frame.
Reserved.
R SCLK is master clock, 256 bits per frame.
BSEL must equal 2, and XCLK must equal 0.
XTAL1, 24.576 MHz, is clock source.
XTAL2, 16.9344 MHz, is clock source.
CLKIN is clock source, and must be 256xFs.
CLKIN is clock source, DFR2-0 select sample
frequency.
R SCLK and FSYNC three-state up to 12 clocks
after D/C goes low.
SCLK and FSYNC three-state immediately
after D/C goes low.
Control Time Slot 4, Test Register
D7 D6 D5 D4 D3 D2 D1 D0
Register
TEST
ENL DAD
Reset (R)
0
0
0
0
0
0
0
0
BIT
DAD
ENL
TEST
NAME
Loopback Mode
Enable Loopback
Testing
Test bits
VALUE
0
1
0
1
FUNCTION
R Digital-Digital Loopback.
Digital-Analog-Digital Loopback.
R Disable.
Enable.
The TEST bits must be written as zero, otherwise
special factory test modes may be invoked.
DS76F2
19
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