GRM188R61E105KA12D 데이터 시트보기 (PDF) - International Rectifier
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GRM188R61E105KA12D
International Rectifier
GRM188R61E105KA12D Datasheet PDF : 45 Pages
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9A Highly Integrated SupIRBuckTM
Single‐Input V-o2lt1a-ge, Synchronous Buck Regulator
PD‐97661
IR3899
half of peak to peak inductor ripple current. The current
limit point will be a function of the inductor value, input
voltage, output voltage and the frequency of operation.
IOCP
ILIMIT
i
2
(2)
IOCP= DC current limit hiccup point
ILIMIT= Current limit Valley Point
Δi=Inductor ripple current
from Rt/Sync pin to Gnd is required to set the free‐running
frequency.
When an external clock is applied to Rt/Sync pin after the
converter runs in steady state with its free‐running
frequency, a transition from the free‐running frequency to
the external clock frequency will happen. This transition is
to gradually make the actual switching frequency equal to
the external clock frequency, no matter which one is
higher. On the contrary, when the external clock signal is
removed from Rt/Sync pin, the switching frequency is also
changed to free‐running gradually. In order to minimize
the impact from these transitions to output voltage, a
diode is recommended to add between the external clock
and Rt/Sync pin, as shown in Figure 9a. Figure 9b shows
the timing diagram of these transitions.
Figure 8: Timing Diagram for
Current Limit Hiccup
Figure 9a: Configuration of External Synchronization
THERMAL SHUTDOWN
Temperature sensing is provided inside IR3899. The trip
threshold is typically set to 145oC. When trip threshold is
exceeded, thermal shutdown turns off both MOSFETs and
resets the internal soft start.
Automatic restart is initiated when the sensed
temperature drops within the operating range. There is
a 20oC hysteresis in the thermal shutdown threshold.
EXTERNAL SYNCHRONIZATION
IR3899 incorporates an internal phase lock loop (PLL)
circuit which enables synchronization of the internal
oscillator to an external clock. This function is important to
avoid sub‐harmonic oscillations due to beat frequency for
embedded systems when multiple point‐of‐load (POL)
regulators are used. A multi‐function pin, Rt/Sync, is used
to connect the external clock. If the external clock is
present before the converter turns on, Rt/Sync pin can be
connected to the external clock signal solely and no other
resistor is needed. If the external clock is applied after the
converter turns on, or the converter switching frequency
needs to toggle between the external clock frequency and
the internal free‐running frequency, an external resistor
Figure 9b: Timing Diagram for Synchronization
to the external clock (Fs1>Fs2 or Fs1<Fs2)
An internal circuit is used to change the PWM ramp slope
according to the clock frequency applied on Rt/Sync pin.
Even though the frequency of the external synchronization
clock can vary in a wide range, the PLL circuit will make
sure that the ramp amplitude is kept constant, requiring no
adjustment of the loop compensation. Vin variation also
affects the ramp amplitude, which will be discussed
separately in Feed‐Forward section.
21 JANUARY 18, 2013 |DATA SHEET | 3.6
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