IDT74FCT163AT(2000) 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT74FCT163AT
(Rev.:2000)
(Rev.:2000)
Integrated Device Technology
IDT74FCT163AT Datasheet PDF : 7 Pages
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IDT54/74FCT163T/AT/CT
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT163T
FCT163AT
FCT163CT
Symbol
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tSU
tH
tSU
tH
tSU
Parameter
Propagation Delay
CP to Qn (PE input HIGH)
Propagation Delay
CP to Qn (PE input LOW)
Propagation Delay
CP to TC
Propagation Delay
CET to TC
Set-up Time HIGH or LOW
Pn to CP
Hold Time HIGH or LOW
Pn to CP
Set-up Time HIGH or LOW
PE or SR to CP
Hold Time HIGH or LOW
PE or SR to CP
Set-up Time HIGH or LOW
CEP ir CET to CP
Condition(1)
CL = 50pF
RL = 500Ω
Ind.
Mil.
Ind.
Mil.
Ind.
Mil.
Min. (2) Max. Min. (2) Max. Min. (2) Max. Min. (2) Max. Min. (2) Max. Min. (2) Max. Unit
2 11 2 11.5 2 7.2 2 7.5 2 5.8 2 6.3 ns
2 9.5 2 10 2 6.2 2 6.5 2 5.8 2 6.3 ns
2 15 2 16.5 2 9.8 2 10.8 2 7.4 2 8.3 ns
1.5 8.5 1.5 9 1.5 5.5 1.5 5.9 1.5 5.2 1.5 5.6 ns
5 — 5.5 — 4 — 4.5 — 4 — 4.5 — ns
1.5 — 2 — 1.5 — 2 — 1.5 — 2 — ns
11.5 — 13.5 — 9.5 — 11.5 — 9.5 — 11.5 — ns
1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns
11.5 — 13 — 9.5 — 11 — 9.5 — 11 — ns
tH
Hold Time HIGH or LOW
CEP ir CET to CP
tW
CP Pulse Width (load)
HIGH or LOW
tW
CP Pulse Width (count)
HIGH or LOW
0 — 0 — 0 — 0 — 0 — 0 — ns
5
—
5
— 4 (3) — 4 (3) — 4 (3) — 4 (3) — ns
7 — 8 — 6 — 7 — 6 — 7 — ns
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This limit is guaranteed but not tested.
5
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