AD1981BLJSTZ 데이터 시트보기 (PDF) - Analog Devices
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AD1981BLJSTZ Datasheet PDF : 32 Pages
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AD1981BL
Parameter
SYNC Period
Setup to Falling Edge of BIT_CLK
Hold from Falling Edge of BIT_CLK
BIT_CLK Rise Time
BIT_CLK Fall Time
SYNC Rise Time
SYNC Fall Time
SDATA_IN Rise Time
SDATA_IN Fall Time
SDATA_OUT Rise Time
SDATA_OUT Fall Time
End of Slot 2 to BIT_CLK, SDATA_IN Low
Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT)
Rising Edge of RESET to High Z Delay
Propagation Delay
RESET Rise Time
Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid
Symbol
tSYNC_PERIOD
tSETUP
tHOLD
tRISECLK
tFALLCLK
tRISESYNC
tFALLSYNC
tRISEDIN
tFALLDIN
tRISEDOUT
tFALLDOUT
tS2_PDOWN
tSETUP2RST
tOFF
Min
5
5
2
2
2
2
2
2
2
2
0
15
Typ
20.8
2.5
4
4
4
4
4
4
4
4
1 Guaranteed but not tested.
2 Output jitter is directly dependent on crystal input jitter.
3 Maximum jitter specification is for noncrystal operation only. Crystal operation maximum is much lower.
Max Unit
ms
ns
ns
6
ns
6
ns
6
ns
6
ns
6
ns
6
ns
6
ns
6
ns
1.0
ms
ns
25
ns
15
ns
50
ns
15
ns
RESET
BIT_CLK
SDATA_IN
tRST_LOW
tRST2CLK
tTRI2ACTV
tTRI2ACTV
Figure 2. Cold Reset Timing (Codec is Supplying the BIT_CLK Signal)
SYNC
BIT_CLK
tSYNC_HIGH
tSYNC2CLK
Figure 3. Warm Reset Timing
Rev. A | Page 6 of 32
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