ADC0820 데이터 시트보기 (PDF) - Philips Electronics
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ADC0820 Datasheet PDF : 14 Pages
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Philips Semiconductors Linear Products
8-Bit, high-speed, µP-compatible A/D converter with
track/hold function
Product specification
ADC0820
AC ELECTRICAL CHARACTERISTICS
VDD = 5V, tR = tF = 20ns, VREF(+) = 5V, VREF(-) = 0V, and TA = 25°C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
Min
tCRD
tACCO
Conversion time for RD mode
Access time (delay from falling edge of
RD to output valid)
Mode=0, Figure 1
Mode=0, Figure 1
tCWR-RD Conversion time for WR-RD mode
Mode=VDD, tWR=600ns, tRD=600ns;
Figures 3a and 3b
Min
tWR
Write time
Max
600
Mode=VDD, Figures 3a and 3b2
tRD
Read time
Min
Mode=VDD, Figures 3a and 3b2
600
tACC1
Access time (delay from falling edge of
RD t o output valid)
Mode=VDD, tRD<tI;
Figure 3b, CL=15pF
CL=100pF
tACC2
Access time (delay from falling edge of
RD t o output valid)
Mode=VDD, tRD>tI;
Figure 3a, CL=15pF
CL=100pF
tI
Internal comparison time
Mode=VDD;
Figures 2 and 3a, CL=50pF
t1H, t0H
Three-state control (delay from rising
edge of RD to Hi-Z state)
RL=1kΩ, CL=10pF
tINTL
tINTH
tINTHWR
Delay from rising edge of WR to falling
edge of INT
Delay from rising edge of RD to rising
edge of INT
Delay from rising edge of WR to rising
edge of INT
Mode=VDD, CL=50pF
tRD>tI; Figure 3a
tRD<tI; Figure 3b
Figures 1, 3a, and 3b,
CL=50pF
Figure 2, CL=50pF
tRDY
tID
tRI
Delay from CS to RDY
Delay from INT to output valid
Delay from RD to INT
Figure 1, CL=50pF, Mode=0
Figure 2
Mode=VDD, tRD<tI;
Figure 3b
tP
Delay from end of conversion to next
conversion
Figures 1, 2, 3a, and 3b2
500
SR
Slew rate, tracking
CVIN
Analog input capacitance
COUT
Logic output capacitance
CIN
Logic input capacitance
NOTES:
1. Unadjusted error includes offset, full-scale, and linearity errors.
2. Accuracy may degrade if tWR or tRD is shorter than the minimum value specified.
3. Typical values are at 25°C and represent most likely parametric norm.
4. Guaranteed but not 100% production tested. These limits are not used to calculate outgoing quality levels.
5. VREF and VIN must be applied after VCC has been turned on to prevent possibility of latching.
LIMITS4
Typ3
Max
1.6
2.5
tCRD+20 tCRD+50
UNIT
µs
ns
1.52
µs
ns
50
µs
ns
190
280
ns
210
320
70
120
ns
90
150
ns
800
1300
ns
100
200
ns
tI
ns
tRD+200 tRD+290
ns
125
225
ns
175
270
ns
50
100
ns
20
50
ns
200
290
ns
ns
0.1
V/µs
45
pF
5
pF
5
pF
August 31, 1994
572
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