AD7866 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
일치하는 목록
AD7866 Datasheet PDF : 25 Pages
| |||
AD7866
TIMING SPECIFICATIONS1(VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.)
Parameter
fSCLK 2
Limit at
TMIN, TMAX
10
20
Unit
kHz min
MHz max
Description
tCONVERT
tQUIET
t2
t33
t43
t5
t6
t7
t84
t94
16 ϫ tSCLK
800
50
10
25
40
0.4 tSCLK
0.4 tSCLK
10
25
10
50
ns max
ns max
ns max
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns max
tSCLK = 1/fSCLK
fSCLK = 20 MHz
Minimum Time between End of Serial Read and Next Falling Edge of CS
CS to SCLK Setup Time
Delay from CS until DOUTA and DOUTB Three-State Disabled
Data Access Time after SCLK Falling Edge. VDRIVE Ն 3 V, CL = 50 pF;
VDRIVE < 3 V, CL = 25 pF
SCLK Low Pulsewidth
SCLK High Pulsewidth
SCLK to Data Valid Hold Time
CS Rising Edge to DOUTA, DOUTB, High Impedance
SCLK Falling Edge to DOUTA, DOUTB, High Impedance
SCLK Falling Edge to DOUTA, DOUTB, High Impedance
NOTES
1Sample tested at 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
2Mark/Space ratio for the CLK input is 40/60 to 60/40.
3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4t8, t9 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo-
lated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times t8 and t9 quoted in the timing characteristics are the true
bus relinquish times of the part and are independent of the bus loading.
Specifications subject to change without notice.
200A
IOL
TO
OUTPUT
PIN
CL
50pF
200A
IOH
1.6V
Figure 1. Load Circuit for Digital Output Timing Specifications
–4–
REV. A
Share Link: 