AD73311AR 데이터 시트보기 (PDF) - Analog Devices
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AD73311AR Datasheet PDF : 36 Pages
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AD73311
Table II. Current Summary (AVDD = DVDD = +5.5 V)
Conditions
Analog Internal Digital External Interface
MCLK
Current Current
Current
Total Current SE ON Comments
ADC On Only
8.5
6
2
16.5
ADC and DAC On 14.5 6
2
22.5
REFCAP On Only 0.8
0
0
1.0
REFCAP and
REFOUT On Only 3.5
0
0
3.5
All Sections Off
0
1.5
0
1.7
All Sections Off
0
0.01
0
0.02
The above values are in mA and are typical values unless otherwise noted.
1 YES
1 YES
0 NO
0 NO
0 YES
0 NO
REFOUT Disabled
REFOUT Disabled
REFOUT Disabled
MCLK Active Levels Equal to
0 V and DVDD
Digital Inputs Static and
Equal to 0 V or DVDD
Table III. Signal Ranges
VREFCAP
VREFOUT
ADC
DAC
Maximum Input Range
at VIN
Nominal Reference Level
Maximum Voltage
Output Swing
Single-Ended
Differential
Nominal Voltage
Output Swing
Single-Ended
Differential
Output Bias Voltage
3 V Power Supply
5VEN = 0
1.2 V ± 10%
1.2 V ± 10%
1.578 V p-p
1.0954 V p-p
1.578 V p-p
3.156 V p-p
1.0954 V p-p
2.1909 V p-p
VREFOUT
5 V Power Supply
5VEN = 0
5VEN = 1
1.2 V
2.4 V
1.2 V
2.4 V
1.578 V p-p
1.0954 V p-p
3.156 V p-p
2.1908 V p-p
1.578 V p-p
3.156 V p-p
1.0954 V p-p
2.1909 V p-p
VREFOUT
3.156 V p-p
6.312 V p-p
2.1908 V p-p
4.3818 V p-p
VREFOUT
TIMING CHARACTERISTICS (AVDD = +3 V ؎ 10%; DVDD = +3 V ؎ 10%; AGND = DGND = 0 V; TA = TMlN to TMAX, unless
otherwise noted)
Parameter
Clock Signals
t1
t2
t3
Serial Port
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
Limit at
TA = –40؇C to +85؇C
61
24.4
24.4
t1
0.4 × t1
0.4 × t1
20
0
10
10
10
10
30
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns max
Description
See Figure 1
MCLK Period
MCLK Width High
MCLK Width Low
See Figures 3 and 4
SCLK Period
SCLK Width High
SCLK Width Low
SDI/SDIFS Setup Before SCLK Low
SDI/SDIFS Hold After SCLK Low
SDOFS Delay from SCLK High
SDOFS Hold After SCLK High
SDO Hold After SCLK High
SDO Delay from SCLK High
SCLK Delay from MCLK
–6–
REV. B
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