AD1981B 데이터 시트보기 (PDF) - Analog Devices
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AD1981B Datasheet PDF : 28 Pages
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AD1981B
SPECIFICATIONS (continued)
Parameter
CLOCK SPECIFICATIONS1
Input Clock Frequency
Recommended Clock Duty Cycle
NOTES
1Guaranteed but not tested.
2Measurements reflect main ADC.
Specifications subject to change without notice.
Min
Typ
Max
24.576
40
50
60
Unit
MHz
%
Parameter
POWER-DOWN STATES*
(Fully Active)
ADC
DAC
ADC + DAC
Mixer
ADC + Mixer
DAC + Mixer
ADC + DAC + Mixer
Standby
Headphone Standby
Set Bits
(No Bits Value)
PR0
PR1
PR1, PR0
PR2
PR2, PR0
PR2, PR1
PR2, PR1, PR0
PR5, PR4, PR3, PR2, PR1, PR0
PR6
DVDD Typ
42
36
29
12
42
36
29
12
0
42
AVDD Typ
51
45
35
28
24
18
9
1.5
0
44
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
*Values presented with VREFOUT not loaded.
Specifications subject to change without notice.
TIMING PARAMETERS (Guaranteed over Operating Temperature Range)
Parameter
Symbol
Min
Typ
Max Unit
RESET Active Low Pulsewidth
RESET Inactive to BIT_CLK Start-Up Delay
SYNC Active High Pulsewidth
SYNC Low Pulsewidth
SYNC Inactive to BIT_CLK Start-Up Delay
BIT_CLK Frequency
BIT_CLK Frequency Accuracy
BIT_CLK Period
BIT_CLK Output Jitter1, 2, 3
BIT_CLK High Pulsewidth
BIT_CLK Low Pulsewidth
SYNC Frequency
SYNC Period
Setup to Falling Edge of BIT_CLK
Hold from Falling Edge of BIT_CLK
BIT_CLK Rise Time
BIT_CLK Fall Time
SYNC Rise Time
SYNC Fall Time
SDATA_IN Rise Time
SDATA_IN Fall Time
SDATA_OUT Rise Time
SDATA_OUT Fall Time
End of Slot 2 to BIT_CLK, SDATA_IN Low
Setup to Trailing Edge of RESET
(Applies to SYNC, SDATA_OUT)
Rising Edge of RESET to Hi-Z Delay
Propagation Delay
RESET Rise Time
Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid
tRST_LOW
tRST2CLK
tSYNC_HIGH
tSYNC_LOW
tSYNC2CLK
tCLK_PERIOD
tCLK_HIGH
tCLK_LOW
tSYNC_PERIOD
tSETUP
tHOLD
tRISECLK
tFALLCLK
tRISESYNC
tFALLSYNC
tRISEDIN
tFALLDIN
tRISEDOUT
tFALLDOUT
tS2_PDOWN
tSETUP2RST
tOFF
162.8
162.8
32.56
32.56
5
5
2
2
2
2
2
2
2
2
0
15
1.0
1.3
19.5
12.288
81.4
750
42
38
48.0
20.8
2.5
4
4
4
4
4
4
4
4
±1
2000
48.84
6
6
6
6
6
6
6
6
1.0
ms
ns
ms
µs
ns
MHz
ppm
ns
ps
ns
ns
kHz
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
25
ns
15
ns
50
ns
15
ns
NOTES
1Guaranteed but not tested.
2Output jitter is directly dependent on crystal input jitter.
3Maximum jitter specification for noncrystal operation only. Crystal operation maximum is much lower.
Specifications subject to change without notice.
–4–
REV. B
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