AD1981B 데이터 시트보기 (PDF) - Analog Devices

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AD1981B

AC ’97 SoundMAX® Codec

Analog Devices 

AD1981B

MADST

Mixer ADC Status Bit. Indicates status of mixer digitizing ADC (left and right channels).

0 = Mixer ADC not ready.

1 = Mixer ADC ready.

2CMIC

MADPD

2-Channel MIC Select. This bit enables simultaneous recording from MIC1 and MIC2 inputs for applications that

use a stereo microphone array. Note that this register works in conjunction with the MS bit in Register 20h.

0 = MIC1 or MIC2 (determined by MS bit) is routed to the record selector’s left and right MIC channels as well

as to the mixer (reset default).

1 = MIC1 is routed to the record selector’s left MIC channel and MIC2 is routed to the record selector’s

right MIC channel. Note that in this mode, the MS bit should be set low and MIC1 can still be enabled into the mixer.

Mixer ADC Power Down. Controls power down for mixer digitizing ADC.

0 = Mixer ADC is powered on (default).

1 = Mixer ADC is powered down.

FMXE

DAM

LODIS

MSPLT

Front DAC into Mixer Enable. Controls the front (main) DAC to mixer mute switches.

0 = Front DAC outputs are allowed to sum into the mixer (reset default).

1 = Front DAC outputs are muted into the mixer (blocked).

Digital Audio Mode. PCM DAC outputs bypass the analog mixer and are sent directly to the codec output.

LINE_OUT Disable. Disables the LINE_OUT pins (L/R), placing them into High Z mode so that the assigned

output audio jack can be shared for input function (or other function).

0 = LINE_OUT pins have normal audio drive capability (reset default).

1 = LINE_OUT pins are placed into High Z mode.

Mute Split. Allows separate mute control bits for Master, Headphone, LINE_IN, CD, AUX, and PCM volume control

registers as well as record gain register.

0 = Both left and right channel mutes are controlled by Bit 15 in the respective registers (reset default).

1 = Bit 15 affects only the left channel mute and Bit 7 affects only the right channel mute.

DACZ

DAC Zero-Fill. Determines DAC data fill under starved conditions.

0 = DAC data is repeated when DACs are starved for data (reset default).

1 = DAC is zero-filled when DACs are starved for data.

Vendor ID Register (Index 7Ch–7Eh)

Reg

No. Name

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

7Ch Vendor ID1 F7 F6 F5 F4 F3 F2 F1 F0 S7 S6 S5 S4 S3 S2 S1 S0 4144h

S[7:0] This register is ASCII encoded to A.

F[7:0] This register is ASCII encoded to D.

Reg

No. Name

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

7Eh Vendor ID2 T7 T6 T5 T4 T3 T2 T1 T0 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 5374h

T[7:0] This register is ASCII encoded to S.

REV[7:0] Vendor specific revision number: The AD1981B assigns 74h to this field.

Table IX. Codec ID and External Clock Selection Table

ID1

ID0

Codec ID

Codec Clocking Source

1

1

(00) Primary

24.576 MHz

(Local Xtal or External into XTL_IN)

1

0

(01) Secondary

12.288 MHz

(External into BIT_CLK)

0

1

(00) Primary

48.000 MHz

(External into XTL_IN)

0

0

(00) Primary

Note that internally, the ID pins have weak pull-ups and are inverted.

14.31818 MHz (External into XTL_IN)

–26–

REV. B

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