74LS670 데이터 시트보기 (PDF) - ON Semiconductor

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74LS670

4 x 4 Register File with 3-State Outputs

ON Semiconductor 

SN74LS670

CONNECTION DIAGRAM DIP (TOP VIEW)

VCC D1 WA WB EW ER Q1 Q2

16 15 14 13 12 11 10 9

NOTE:

The Flatpak version has the same

pinouts (Connection Diagram) as

the Dual In-Line Package.

1 2 3 4 56 78

D2 D3 D4 RB RA Q4 Q3 GND

PIN NAMES

D1 – D4

WA, WB

EW

RA, RB

ER

Q1 – Q4

Data Inputs

Write Address Inputs

Write Enable (Active LOW) Input

Read Address Inputs

Read Enable (Active LOW) Input

Outputs

NOTES:

a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.

LOADING (Note a)

HIGH

LOW

0.5 U.L.

0.5 U.L.

1.0 U.L.

0.5 U.L.

1.5 U.L.

65 U.L.

0.25 U.L.

0.25 U.L.

0.5 U.L.

0.25 U.L.

0.75 U.L.

15 U.L.

LOGIC SYMBOL

12 15 1 2 3

14

WA EW D1 D2 D3 D4

13

WB

5

RA

4

RB ER Q1 Q2 Q3 Q4

11 10 9 7 6

VCC = PIN 16

GND = PIN 8

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