74173 데이터 시트보기 (PDF) - Hitachi -> Renesas Electronics
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74173 Datasheet PDF : 9 Pages
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HD74HC173
4-bit D-type Register (with 3-state Outputs)
Description
The four D type Flip-Flops operate synchronously from a common clock. The 3-state outputs allow the
device to be used in bus organized systems. The outputs are placed in the 3-stage mode when either of the
output disable pins are in the logic high level.
The input disable allows the flip-flops to remain in their present states without having to disrupt the clock.
If either of the 2 input disables are taken to a logic high level, the Q outputs are fed back to the inputs,
forcing the flip-flops to remain in the same state. Clearing is enabled by taking the clear input to a logic
high level. The data outputs change state on the positive going edge of the clock.
Features
• High Speed Operation: tpd (Clock to Q) = 14 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Inputs
Data Enable
Clear
Clock
G1
G2
Data D
Output Q
H
X
X
X
X
L
L
L
X
X
X
Q0
L
H
X
X
Q0
L
X
H
X
Q0
L
L
L
L
L
L
L
L
H
H
Note: When either M or N (or both) is (are) high the output is disabled to the high-impedance state;
however sequential operation of the flip-flops is not affected.
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