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33702

3.0 A Switch-Mode Power Supply with Linear Regulator

Motorola => Freescale 

Freescale Semiconductor, Inc.

DYNAMIC ELECTRICAL CHARACTERISTICS (continued)

Characteristics noted under conditions -40°C ≤ TJ ≤ 125°C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical

application circuit (see Figure 20) unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

LINEAR REGULATOR (LDO)

LDO Output Current Slew Rate

ISR

–

TBD

–

mA/µs

Fault Condition Timeout

tFAULT

–

1.0

–

ms

Retry Timer Cycle

tRet

–

100

–

ms

SCA, SCL PIN, I2C BUS (STANDARD)

SCL Clock Frequency

fSCL

0

–

100

kHz

Bus Free Time Between a STOP and a START Condition

tBUF

4.7

–

–

µs

Hold Time (Repeated) START Condition (After this period, the first clock pulse

tHD-STA

is generated.)

4.0

–

µs

–

Low Period of the SCL Clock

tLOW

4.7

–

–

µs

High Period of the SCL Clock

tHIGH

4.0

–

–

µs

SDA Fall Time from VIH_MAX to VIL_MIN, Bus Capacitance 10 pF to 400 pF,

tF

3.0 mA Sink Current

ns

–

–

250

Setup Time for a Repeated START Condition

tSU-STA

4.7

–

–

µs

Data Hold Time for I2C bus devices (Note 10), (Note 11)

tHD-DAT

0

–

–

µs

Data Setup Time

tSU-DAT

250

–

–

ns

Setup Time for STOP Condition

tSU-STO

4.0

–

–

µs

Capacitive Load for Each Bus Line

CB

–

–

400

pF

Notes

10. Design Information only. Not production tested.

11. The device provides an internal hold time of at least 300 ns for the SDA signal (refer to the VIH_MIN of the SCL signal) to bridge the undefined

region of the falling edge of SCL.

Timing Diagram

tHD-STA

tHD-STA

tHD-DAT

tSU-DAT

tSU-STA

Figure 2. Definition of Time on the I2C Bus

MOTOROLA ANALOG INTEGRATED CIFRCoUrITMDoErVeICEInDfAoTrAmation On This Product,

Go to: www.freescale.com

tSU-STO

33702

11

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