LXT332PE 데이터 시트보기 (PDF) - LevelOne

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LXT332PE

Dual T1/E1 Line Interface Unit with Crystal-less Attenuation

LevelOne 

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TTIP0 AO Transmit Tip and Ring - Port 0. The tip and ring pins for each port are dif-

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TRING0 AO ferential driver outputs designed to drive a 35 - 200 Ω load. Line matching

resistors and transformers can be selected to give the desired pulse height.

See Figures 19 through 21.

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TGND0 – Ground. Ground return for power supply TVCC0.

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TVCC0 I + 5 volt power supply input for the port 0 transmit driver. TVCC0 must

not vary from TVCC1 or VCC by more than ± 0.3 V.

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DFM

O Driver Fail Monitor. This signal goes High to indicate a driver output short

in one or both ports.

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PS0

I Port Select - Port 0. This input accesses the serial interface registers for

port 0. For each read or write operation, PS must transition from High to

Low, and remain Low.

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PD0

DO Pattern Detect - Port 0. Unless the QRSS function is selected by the VCQE

pin, PD0 functions as an AIS alarm indicator. The AIS pattern is detected by

the receiver, independent of any loopback mode. AIS goes High when less

than three zeros have been detected in any string of 2048 bits. AIS returns

Low when the received signal contains more than three zeros in 2048 bits.

(LOS is available via the SIO register and interrupt.)

If the QRSS function is enabled by the VCQE pin, PD0 remains High until

pattern sync is reached with the received signal. Once pattern lock is

obtained, PD0 goes Low. (The sync/out-of-sync criteria is less than 3/4

errors in 128 bits.) After sync acquisition, bit errors cause PD0 to go High

for half a clock cycle. This output can be used to trigger an external error

counter.

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RTIP0 DI Receive Tip and Ring - Port 0. RTIP and RRING comprise the receive line

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RRING0 DI interface. This input pair should be connected to the line through a center-

tapped 1:2 transformer.

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CLKE DI Clock Edge Select. When CLKE is High, RPOS/RNEG or RDATA out-

puts are valid on the falling edge of RCLK, and SDO is valid on the rising

edge of SCLK. When CLKE is Low, RPOS/RNEG or RDATA outputs are

valid on the rising edge of RCLK, and SDO is valid on the falling edge of

SCLK.

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RRING1 AI Receive Tip and Ring - Port 1. RTIP and RRING comprise the receive line

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RTIP1 AI interface. This input pair should be connected to the line through a center-

tapped 1:2 transformer.

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PD1

DO Pattern Detect - Port 1. Reports AIS and QRSS pattern reception. See

PD0 signal description for details.

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SDI

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PS1

DI Port Select - Port 1. This input accesses the serial interface registers for

port 1. For each read or write operation, PS must transition from High to

Low, and remain Low.

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TRING1 AO Transmit Tip and Ring - Port 1. The tip and ring pins for each port are dif-

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TTIP1 AO ferential driver outputs designed to drive a 35 - 200 Ω load. Line matching

resistors and transformers can be selected to give the desired pulse height.

See Figures 13 through 15.

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