MG64P 데이터 시트보기 (PDF) - Oki Electric Industry

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MG64P

0.25µm Embedded DRAM/Customer Structured Arrays

Oki Electric Industry 

––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– s MG63P/64P/65P s

More information on OKI’s floorplanning capabilities is available in Oki’s Application Note, Using Oki’s

Floorplanner: Standalone Operation and Links to Synopsys.

Initial Synthesis

Constraints

Gate Level

Netlist

(EDIF)

HDL Entry

Synthesis

No

Constraints Met?

Yes

Initial Floorplan

Incremental

Optimization with

Physical Information

No

Constraints Met?

Yes

Invoke Import on

Floorplanner

Incremental

Floorplan

PDEF

(Synopsis)

Gate Level

Netlist

(EDIF)

DSPF/Oki RC/

PDEF (Synopsys)

Wire Load Model (Synopsys)

Net Capacitance (Synopsys

Script (Synopsys)

Delay

(SDF)

= In Synopsys DC/DA

= In Floorplanner

Invoke Export on

Floorplanner

Invoke Delay

Load

Back-Annotation Files

No

Constraints Met?

Yes

To Simulation and P&R

Timing Optimization

Figure 15. LSF System Design Flow

IEEE JTAG Boundary Scan Support

Boundary scan offers efficient board-level and chip-level testing capabilities. Benefits resulting from

incorporating boundary-scan logic into a design include:

• Improved chip-level and board-level testing and failure diagnostic capabilities

• Support for testing of components with limited probe access

• Easy-to-maintain testability and system self-test capability with on-board software

• Capability to fully isolate and test components on the scan path

• Built-in test logic that can be activated and monitored

• An optional Boundary Scan Identification (ID) Register

Oki Semiconductor

15

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