HD74ACT112 데이터 시트보기 (PDF) - Hitachi -> Renesas Electronics

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HD74ACT112

Dual JK Negative Edge-Triggered Flip-Flop

Hitachi -> Renesas Electronics 

HD74AC112/HD74ACT112

Logic Symbol

4

10

3

SD1

J1

Q1

5 11

SD2

J2

Q2

9

1 CP1

13 CP2

2

K1 CD1 Q1

6 12 K2 CD2 Q2

7

15

VCC = Pin16 14

GND = Pin8

Pin Names

J1, J2, K1, K2

CP1, CP2

CD1, CD2

SD1, SD2

Q1, Q2, Q1, Q 2

Data Inputs

Clock Pulse Inputs (Active Falling Edge)

Direct Clear Inputs (Active Low)

Direct Set Inputs (Active Low)

Outputs

Asynchronous Inputs:

Low input to SD sets Q to High level

Low input to CD sets Q to Low level

Clear and Set are independent of clock

Simultaneous Low on CD and SD makes both Q and Q High

2

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