M74HC73(1992) 데이터 시트보기 (PDF) - STMicroelectronics

부품명

상세내역

일치하는 목록

M74HC73
(Rev.:1992)

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

STMicroelectronics 

M54HC73

M74HC73

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

. HIGH SPEED

fMAX = 75 MHz (TYP.) AT VCC = 5 V

. LOW POWER DISSIPATION

ICC = 2 µA (MAX.) AT TA = 25 °C

. HIGH NOISE IMMUNITY

VNIH = VNIL = 28 % VCC (MIN.)

. OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

. SYMMETRICAL OUTPUT IMPEDANCE

IOH = IOL = 4 mA (MIN.)

. BALANCED PROPAGATION DELAYS

tPLH = tPHL

. WIDE OPERATING VOLTAGE RANGE

VCC (OPR) = 2 V TO 6 V

. PIN AND FUNCTION COMPATIBLE WITH

54/74LS73

B1R

(Plastic Package)

F1R

(Ceramic Package)

M 1R

(Micro Package)

C1R

(Chip Carrier)

ORDER CODES :

M54HC73F1R

M 74H C7 3M 1R

M 74HC 73 B1 R

M 74H C7 3C 1R

DESCRIPTION

The M54/74HC73 is a high speed CMOS DUAL J-K

FLIP FLOP WITH CLEAR fabricated in silicon gate

C2MOS technology. It has the same high speed per-

formance of LSTTL combined with true CMOS low

power consumption. Depending on the logic level

applied to J and K inputs, this device changes state

on the negative going transition of clock input pulse

(CK). The clear function is accomplished inde-

pendently of the clock condition when the clear input

(CLR) is taken low. All inputs are equipped with pro-

tection circuits against static discharge and transient

excess voltage.

INPUT AND OUTPUT EQUIVALENT CIRCUIT

PIN CONNECTIONS (top view)

October 1992

NC =

No Internal

Connection

1/11

Share Link: