NCP1216P133G 데이터 시트보기 (PDF) - ON Semiconductor
부품명
상세내역
일치하는 목록
NCP1216P133G Datasheet PDF : 18 Pages
| |||
NCP1216, NCP1216A
depends on the startup sequence of your system, i.e. when
you first apply the power to the IC. The corresponding
transient fault duration due to the output capacitor charging
must be less than the time needed to discharge from 12.2 V
to 10 V, otherwise the supply will not properly start. The test
consists in either simulating or measuring in the lab how
much time the system takes to reach the regulation at full
load. Let’s suppose that this time corresponds to 6ms.
Therefore a VCC fall time of 10 ms could be well
appropriated in order to not trigger the overload detection
circuitry. If the corresponding IC consumption, including
the MOSFET drive, establishes at 2.9 mA, we can calculate
the required capacitor using the following formula:
Dt
+
DV·C
i
(eq. 19)
with DV = 2.2 V. Then for a wanted Dt of 30 ms, C equals
39.5 mF or a 68 mF for a standard value (including ±20%
dispersions). When an overload condition occurs, the IC
blocks its internal circuitry and its consumption drops to
350 mA typical. This happens at VCC = 10 V and it remains
stuck until VCC reaches 5.6 V: we are in latchoff phase.
Again, using the selected 68 mF and 350 mA current
consumption, this latchoff phase lasts: 780 ms.
Protecting the Controller Against Negative Spikes
As with any controller built upon a CMOS technology, it
is the designer’s duty to avoid the presence of negative
spikes on sensitive pins. Negative signals have the bad habit
to forward bias the controller substrate and induce erratic
behaviors. Sometimes, the injection can be so strong that
internal parasitic SCRs are triggered, engendering
irremediable damages to the IC if a low impedance path is
offered between VCC and GND. If the current sense pin is
often the seat of such spurious signals, the high−voltage pin
can also be the source of problems in certain circumstances.
During the turn−off sequence, e.g. when the user unplugs the
power supply, the controller is still fed by its VCC capacitor
and keeps activating the MOSFET ON and OFF with a peak
current limited by Rsense. Unfortunately, if the quality
coefficient Q of the resonating network formed by Lp and
Cbulk is low (e.g. the MOSFET Rdson + Rsense are small),
conditions are met to make the circuit resonate and thus
negatively bias the controller. Since we are talking about ms
pulses, the amount of injected charge, (Q = I * t),
immediately latches the controller that brutally discharges
its VCC capacitor. If this VCC capacitor is of sufficient value,
its stored energy damages the controller. Figure 26 depicts
a typical negative shot occurring on the HV pin where the
brutal VCC discharge testifies for latchup.
0
VCC
5 V/DIV
10 ms/DIV
Vlatch
1 V/DIV
Figure 26. A Negative Spike Takes Place on the Bulk Capacitor at the Switch−off Sequence
Simple and inexpensive cures exist to prevent from
internal parasitic SCR activation. One of them consists in
inserting a resistor in series with the high−voltage pin to
keep the negative current to the lowest when the bulk
becomes negative (Figure 27). Please note that the negative
spike is clamped to (−2 * Vf) due to the diode bridge. Also,
the power dissipation of this resistor is extremely small since
it only heats up during the startup sequence.
Another option (Figure 28) consists in wiring a diode
from VCC to the bulk capacitor to force VCC to reach
VCCON sooner and thus stops the switching activity before
the bulk capacitor gets deeply discharged. For security
reasons, two diodes can be connected in series.
www.onsemi.com
14
Share Link: 