74LVC125ABQ-Q100(2013) 데이터 시트보기 (PDF) - Nexperia B.V. All rights reserved

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74LVC125ABQ-Q100
(Rev.:2013)

Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

Nexperia B.V. All rights reserved 

Nexperia

74LVC125A-Q100

Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

10. Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8.

Symbol Parameter

Conditions

40 C to +85 C

Min Typ[1] Max

tpd

propagation delay nA to nY; see Figure 6

[2]

VCC = 1.2 V

-

12.0

-

VCC = 1.65 V to 1.95 V

1.5 5.4 11.0

VCC = 2.3 V to 2.7 V

1.0 2.9 5.7

VCC = 2.7 V

1.5 2.8 5.5

ten

enable time

VCC = 3.0 V to 3.6 V

nOE to nY; see Figure 7

1.0 2.5 4.8

[2]

VCC = 1.2 V

-

16.0

-

VCC = 1.65 V to 1.95 V

1.0 5.0 12.2

VCC = 2.3 V to 2.7 V

0.5 2.9 6.8

VCC = 2.7 V

1.5 3.1 6.6

tdis

disable time

VCC = 3.0 V to 3.6 V

nOE to nY; see Figure 7

1.0 2.3 5.4

[2]

VCC = 1.2 V

-

7.0

-

VCC = 1.65 V to 1.95 V

2.2 4.6 7.5

VCC = 2.3 V to 2.7 V

0.5 2.6 4.2

VCC = 2.7 V

1.5 3.1 5.0

tsk(o)

CPD

output skew time

power dissipation

capacitance

VCC = 3.0 V to 3.6 V

VCC = 3.0 V to 3.6 V

per buffer; VI = GND to VCC

VCC = 1.65 V to 1.95 V

1.0 3.2 4.6

[3]

-

-

1.0

[4]

-

6.0

-

VCC = 2.3 V to 2.7 V

-

9.4

-

VCC = 3.0 V to 3.6 V

-

12.4

-

40 C to +125 C Unit

Min

Max

-

- ns

1.5

12.8 ns

1.0

6.7 ns

1.5

7.0 ns

1.0

6.0 ns

-

- ns

1.0

14.2 ns

0.5

7.9 ns

1.5

8.5 ns

1.0

7.0 ns

-

- ns

2.2

8.7 ns

0.5

5.0 ns

1.5

6.5 ns

1.0

6.0 ns

-

1.5 ns

-

- pF

-

- pF

-

- pF

[1] Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.

[2] tpd is the same as tPLH and tPHL.

ten is the same as tPZL and tPZH.

tdis is the same as tPLZ and tPHZ.

[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

[4] CPD is used to determine the dynamic power dissipation (PD in W).

PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:

fi = input frequency in MHz; fo = output frequency in MHz

CL = output load capacitance in pF

VCC = supply voltage in Volts

N = number of inputs switching

(CL  VCC2  fo) = sum of the outputs.

74LVC125A_Q100

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 4 April 2013

© Nexperia B.V. 2017. All rights reserved

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