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MC74HC597A
ON Semiconductor
MC74HC597A Datasheet PDF : 12 Pages
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MC74HC597A
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
VCC
– 55 to
V
25_C v 85_C v 125_C Unit
tsu
Minimum Setup Time, Parallel Data inputs A−H to Latch Clock
(Figure 7)
2.0
70
80
90
ns
3.0
40
45
50
4.5
15
19
24
6.0
13
16
20
tsu
Minimum Setup Time, Serial Data Input SA to Shift Clock
(Figure 8)
2.0
70
80
90
ns
3.0
40
45
50
4.5
15
19
24
6.0
13
16
20
tsu
Minimum Setup Time, Serial Shift/Parallel Load to Shift Clock
(Figure 9)
2.0
70
80
90
ns
3.0
40
45
50
4.5
15
19
24
6.0
13
16
20
th
Minimum Hold Time, Latch Clock to Parallel Data Inputs A−H
(Figure 7)
2.0
15
20
30
ns
3.0
10
15
25
4.5
2
3
5
6.0
2
3
4
th
Minimum Hold Time, Shift Clock to Serial Data Input SA
(Figure 8)
2.0
2
2
2
ns
3.0
2
2
2
4.5
2
2
2
6.0
2
2
2
trec
Minimum Recovery Time, Reset Inactive to Shift Clock
(Figure 5)
2.0
70
80
90
ns
3.0
40
45
50
4.5
15
19
24
6.0
13
16
20
tw
Minimum Pulse Width, Latch Clock and Shift Clock
(Figures 3 and 4)
2.0
60
70
80
ns
3.0
35
40
45
4.5
12
15
19
6.0
10
13
16
tw
Minimum Pulse Width, Reset
(Figure 5)
2.0
60
70
80
ns
3.0
35
40
45
4.5
12
15
19
6.0
10
13
16
tw
Minimum Pulse Width, Serial Shift/Parallel Load
(Figure 6)
2.0
60
70
80
ns
3.0
35
40
45
4.5
12
15
19
6.0
10
13
16
tr, tf
Maximum Input Rise and Fall Times
(Figure 3)
2.0
1000
1000
1000
ns
3.0
800
800
800
4.5
500
500
500
6.0
400
400
400
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High−Speed CMOS Data Book (DL129/D).
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