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74HC597 데이터 시트보기 (PDF) - NXP Semiconductors.

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74HC597
NXP
NXP Semiconductors. NXP
74HC597 Datasheet PDF : 23 Pages
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NXP Semiconductors
74HC597; 74HCT597
8-bit shift register with input flip-flops
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 14.
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max
Min
Max
th
hold time Dn to STCP; see
Figure 12
VCC = 4.5 V
PL, DS to SHCP; see
Figure 12
5 1 -
5
-
5
-
ns
VCC = 4.5 V
5 2 -
5
-
5
-
ns
fmax
maximum SHCP; see Figure 8
frequency
VCC = 4.5 V
30 75
-
24
-
20
-
MHz
VCC = 5.0 V; CL = 15 pF
-
83 -
-
-
-
-
MHz
CPD
power
CL = 50 pF; f = 1 MHz;
[3] -
32 -
-
-
-
-
pF
dissipation VI = GND to VCC 1.5 V
capacitance
[1] tpd is the same as tPLH and tPHL.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
11. Waveforms
9,
67&36+&3
LQSXW
*1'
92+
4RXWSXW
92/
IPD[
90
W:
W3/+
90
W3+/
DDD
Fig 8.
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Shift clock and storage clock inputs to output, propagation delays, pulse widths and maximum clock
frequency
74HC_HCT597
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 15 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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