74HC595 데이터 시트보기 (PDF) - ON Semiconductor
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74HC595
ON Semiconductor
74HC595 Datasheet PDF : 13 Pages
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74HC595
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
Parameter
VCC
Guaranteed Limit
(V) – 55 to 25_C v 85_C v 125_C Unit
fmax Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 7)
2.0
6.0
3.0
15
4.5
30
6.0
35
4.8
4.0
MHz
10
8.0
24
20
28
24
tPLH,
tPHL
Maximum Propagation Delay, Shift Clock to SQH
(Figures 1 and 7)
2.0
140
3.0
100
4.5
28
6.0
24
175
210
ns
125
150
35
42
30
36
tPHL Maximum Propagation Delay, Reset to SQH
(Figures 2 and 7)
2.0
145
3.0
100
4.5
29
6.0
25
180
220
ns
125
150
36
44
31
38
tPLH,
tPHL
Maximum Propagation Delay, Latch Clock to QA − QH
(Figures 3 and 7)
2.0
140
3.0
100
4.5
28
6.0
24
175
210
ns
125
150
35
42
30
36
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to QA − QH
(Figures 4 and 8)
2.0
150
3.0
100
4.5
30
6.0
26
190
225
ns
125
150
38
45
33
38
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to QA − QH
(Figures 4 and 8)
2.0
135
3.0
90
4.5
27
6.0
23
170
205
ns
110
130
34
41
29
35
tTLH,
tTHL
Maximum Output Transition Time, QA − QH
(Figures 3 and 7)
2.0
60
3.0
23
4.5
12
6.0
10
75
90
ns
27
31
15
18
13
15
tTLH,
tTHL
Maximum Output Transition Time, SQH
(Figures 1 and 7)
2.0
75
3.0
27
4.5
15
6.0
13
95
110
ns
32
36
19
22
16
19
Cin Maximum Input Capacitance
−
10
10
10
pF
Cout Maximum Three−State Output Capacitance (Output in
High−Impedance State), QA − QH
−
15
15
15
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD Power Dissipation Capacitance (Per Package)*
300
pF
* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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