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MC10H131FN Datasheet PDF : 4 Pages
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual D Type Master-Slave
Flip-Flop
MC10H131
The MC10H131 is a MECL 10H part which is a functional/pinout duplication
of the standard MECL 10K family part, with 100% improvement in clock speed
and propagation delay and no increase in power–supply current.
• Propagation Delay, 1.0 ns Typical
• Power Dissipation, 235 mW Typical
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K–Compatible
MAXIMUM RATINGS
Characteristic
Symbol
Rating
Unit
Power Supply (VCC = 0)
Input Voltage (VCC = 0)
Output Current — Continuous
— Surge
VEE
–8.0 to 0
Vdc
VI
0 to VEE
Vdc
Iout
50
mA
100
Operating Temperature Range
Storage Temperature Range — Plastic
— Ceramic
TA
0 to +75
°C
Tstg
–55 to +150
°C
–55 to +165
°C
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)
0°
25°
75°
Characteristic
Symbol Min Max Min Max Min Max Unit
Power Supply Current
Input Current High
Pins 6, 11
Pin 9
Pins 7, 10
Pins 4, 5, 12, 13
IE
—
62
—
56
—
62
mA
IinH
µA
—
530
—
310
—
310
—
660
—
390
—
390
—
485
—
285
—
285
—
790
—
465
—
465
Input Current Low
High Output Voltage
Low Output Voltage
High Input Voltage
Low Input Voltage
AC PARAMETERS
IinL
VOH
VOL
VIH
VIL
0.5
—
0.5
—
0.3
—
µA
–1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc
–1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc
–1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc
–1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc
Propagation Delay
Clock, CE
Set, Reset
tpd
ns
0.8
1.6
0.8
1.7
0.8
1.8
0.6
1.6
0.7
1.7
0.7
1.8
Rise Time
tr
0.6
2.0
0.6
2.0
0.6
2.2
ns
Fall Time
tf
0.6
2.0
0.6
2.0
0.6
2.2
ns
Set–up Time
tset
0.7
—
0.7
—
0.7
—
ns
Hold Time
thold
0.8
—
0.8
—
0.8
—
ns
Toggle Frequency
ftog
250
—
250
—
250
—
MHz
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 Iinear fpm is maintained. Outputs are terminated through
a 50–ohm resistor to –2.0 volts.
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
LOGIC DIAGRAM
S1 5
D1 7
CE1 6
Q1
2
Q1
3
R1 4
CC 9
R2 13
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
CE2 11
D2 10
Q2
14
Q2
15
S2 12
RS TRUTH TABLE
R
S
Qn+1
L
L
Qn
L
H
H
H
L
L
H
H
N.D.
CLOCKED TRUTH TABLE
C
D
Qn+1
L
X
Qn
H
L
L
H
H
H
C = CE + CC
N.D. = Not Defined
A clock H is a clock transition
from a low to a high state.
DIP
PIN ASSIGNMENT
VCC1
1
Q1
2
Q1
3
R1
4
S1
5
CE1
6
D1
7
VEE
8
16 VCC2
15 Q2
14 Q2
13 R2
12 S2
11
CE2
10 D2
9
CC
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
3/93
© Motorola, Inc. 1996
2–69
REV 5
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