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SL74HC74

Dual D Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS

System Logic Semiconductor 

SL74HC74

Dual D Flip-Flop with Set and Reset

High-Performance Silicon-Gate CMOS

The SL74HC74 is identical in pinout to the LS/ALS74. The device

inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LS/ALSTTL outputs.

This device consists of two D flip-flops with individual Set, Reset,

and Clock inputs. Information at a D-input is transferred to the

corresponding Q output on the next positive going edge of the clock

input. Both Q and Q outputs are available from each flip-flop. The Set

and Reset inputs are asynchronous.

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

ORDERING INFORMATION

SL74HC74N Plastic

SL74HC74D SOIC

TA = -55° to 125° C for all packages

LOGIC DIAGRAM

PIN ASSIGNMENT

PIN 14 =VCC

PIN 7 = GND

SLS

System Logic

Semiconductor

FUNCTION TABLE

Inputs

Outputs

Set Reset Clock Data Q

Q

L

H

X

X

H

L

H

L

X

X

L

H

L

L

X

X

H*

H*

H

H

H

H

L

H

H

L

L

H

H

H

L

X No Change

H

H

H

X No Change

H

H

X No Change

*Both outputs will remain high as long as Set

and Reset are low, but the output states are

unpredictable if Set and Reset go high

simultaneously.

X = don’t care

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