MC74HC75D 데이터 시트보기 (PDF) - Motorola => Freescale
부품명
상세내역
일치하는 목록
MC74HC75D Datasheet PDF : 5 Pages
| |||
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual 2-Bit Transparent Latch
High–Performance Silicon–Gate CMOS
The MC74HC75 is identical in pinout to the LS75. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device consists of two independent 2–bit transparent latches. Each
latch stores the input data while Latch Enable is at a logic low. The outputs
follow the data inputs when Latch Enable is at a logic high.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 80 FETs or 20 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
2, 6
D0
3, 7
D1
2–BIT
TRANSPARENT
LATCH
16, 10 Q0
1, 11 Q0
15, 9 Q1
14, 8 Q1
LATCH 13, 4
ENABLE
PIN 5 = VCC
PIN 12 = GND
MC74HC75
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
ORDERING INFORMATION
MC74HCXXN
MC74HCXXD
Plastic
SOIC
PIN ASSIGNMENT
Q0a 1
D0a 2
D1a 3
LEb 4
VCC 5
D0b 6
D1b 7
Q1b 8
16 Q0a
15 Q1a
14 Q1a
13 LEa
12 GND
11 Q0b
10 Q0b
9 Q1b
FUNCTION TABLE
Inputs
Latch
D Enable
L
H
H
H
X
L
Outputs
Q
Q
L
H
H
L
Q0
Q0
X = don’t care
Q0 = latched data
10/95
© Motorola, Inc. 1995
1
REV 6
Share Link: 