GT30F124 데이터 시트보기 (PDF) - Toshiba
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GT30F124 Datasheet PDF : 16 Pages
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2 IGBT Technical Overview
Prior to the development of IGBTs, power MOSFETs were used for power amplifier applications which require high input impedance
and fast switching. However, at high voltages, the on-state resistance rapidly increases as the breakdown voltage increases. It is
thus difficult to improve the conduction loss of power MOSFETs.
On the other hand, the IGBT structure consists of a pnp bipolar transistor and a collector contact made on the p+ layer. The IGBT
has a low on-state voltage drop due to conductivity modulation.
The following figure shows the VCE(sat) curve of a soft-switching 900-V IGBT. Toshiba has offered IGBTs featuring fast switching by
using carrier lifetime control techniques. Now, Toshiba offers even faster IGBTs with optimized carrier injection into the collector p+
layer.
In the future, Toshiba will launch IGBTs with varied characteristics optimized for high-current-conduction and high-frequency-
switching applications. The improvements in IGBTs will be spurred by optimized wafers, smaller pattern geometries and improved
carrier lifetime control techniques.
900-V IGBT for Soft-Switching
2.8
2.6
2.4
2.2
2.0
Ta = 25˚C
1.8
High-speed: GT60M323
High-speed: GT50N322A(1000V)
Ta = 125˚C
Low-VCE(sat): GT60M303
1.6
1.4
0
GT60M324
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Eoff(mJ) @VCC = 140 V, IC = 50 A, VGG = 20 V, RG = 10 Ω, C = 0.33 μF, L = 30 μH
Discrete IGBT Development Trends
1200 V
(1) High ruggedness (3rd gen): Low VCE(sat) and high ruggedness due to optimized carrier injection and thinner wafers
(2) Soft switching (5th gen): Low VCE(sat) due to trench gate structure
(3) Soft switching (6.5th gen): RC structure
900 to
1500 V
(1) Soft switching (4th gen): Low VCE(sat) due to trench gate structure
(2) Soft switching (5th gen): Low VCE(sat) due to optimized carrier injection and trench gate structure
(3) Soft switching (6th gen): Thinner wafers and finer process geometries
(4) Soft switching (6.5th gen): RC structure
(1) High ruggedness (3rd gen): Low VCE(sat) and high ruggedness due to optimized carrier injection and thinner wafers
600 V
(2) Fast switching (4th gen): High speedy tf due to optimized carrier injection
(4) Low VCE(sat) (6th gen): Thinner wafers
and finer process geometries
(3) Soft switching (4th gen): Low VCE(sat) due to trench gate structure
(5) Soft switching (5th gen): Thinner wafers
(6) Soft switching (6th gen): Thinner wafers and finer
process geometries
400 V
(1) Strobe flashes (5th gen): Low VCE(sat) due to trench gate structure
(2) Strobe flashes (6th gen): High current due to trench gate structure and optimized wafers
(3) Strobe flashes (7th gen): High current due to optimized wafers and finer process geometries
(1) Plasma displays (4th gen): Low VCE(sat) due to trench gate structure and high IC due to lifetime control
300 to
400 V
(2) Plasma displays (5th gen): Low turn-on loss due to finer process geometries
(3) Plasma displays (6th gen): Low turn-on loss due to optimized wafers and finer process geometries
(4) Plasma displays (7th gen): Thinner
wafers and finer process geometries
Year
2006
2008
2010
2012
–3–
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