CXD1915R 데이터 시트보기 (PDF) - Sony Semiconductor
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CXD1915R Datasheet PDF : 50 Pages
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CXD1915R
Pin
No.
Symbol
46 AVDD1
47 AVSS1
48 C-OUT
49 VB
50 VG
51 Y-OUT
52 AVDD2
53 AVSS2
54 B-OUT
55 AVSS4
56 G-OUT
57 AVDD3
58 AVSS3
59 R-OUT
60 VSS8
61 TVSYNC
62 TD8
63 TD9
64 TD10
65 VDD4
66 XTEST
67
OSDSW/
XTEST1
68
ROSD/
XTEST2
69
GOSD/
XTEST3
70
BOSD/
XTEST4
71 XTEST5
72 SYNCM
73 PIXCON
74 VSS9
75 TDI
I/O
Description
— Analog power supply.
— Analog ground.
O 10-bit DAC output. This pin outputs the chroma (C) signal.
O Connect to ground via a capacitor of approximately 0.1µF.
O Connect to analog power supply via a capacitor of approximately 0.1µF.
O 10-bit DAC output. This pin outputs the luminance (Y) signal.
— Analog power supply.
— Analog ground.
O 10-bit DAC output. This pin outputs the B and U signals.
— Analog ground.
O 10-bit DAC output. This pin outputs the G and Y signals.
— Analog power supply.
— Analog ground.
O 10-bit DAC output. This pin outputs the R and V signals.
— Digital ground.
I Test pin. This pin is pulled up. Normally this pin should be open.
I/O Test data inputs/outputs. These pins should be open.
I/O In test mode, these are used for the internal circuit test data bus.
I/O The test data bus is available only for the device vendor.
— Digital power supply.
I
Test mode control. This pin is pulled up.
Normally this pin should be open.
I
These pins are pulled up. The functions of these pins are selected by XTEST
I (Pin 66).
When XTEST = High, these are OSD data inputs.
I When XTEST = Low, these are test mode control inputs.
The test mode is available only for the device vendor.
I
I Test pin. This pin is pulled up. Normally this pin should be open.
Master/slave switching. This pin is pulled up.
I When SYNCM = High, the CXD1915R is set to master mode.
When SYNCM = Low, the CXD1915R is set to slave mode.
I
Control register bit "PIX_EN" default value control.
This pin is pulled up.
— Digital ground.
I Test mode control input. This pin is pulled up.
–5–
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