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SAA7500

Digital satellite radio broadcasting tuner decoder (SAT-2)

Philips Electronics 

Philips Semiconductors

Digital satellite radio broadcasting tuner

decoder (SAT-2)

Product specification

SAA7500

FUNCTIONAL DESCRIPTION

General

The SAA7500 has been designed to decode 16 stereo channel sound broadcasting signals in accordance with the

German standard - Technische Richtlinie ARD/ZDF Nr. 3R1. The channel carrying the sound broadcast programme

is selected and converted into an intermediate frequency by a frontend. The signal is then amplified and demodulated

(4 PSK (Phase Shift Keying) with carrier recovery). The outputs from the demodulator are two differential coded signals

that are input into the SAA7500. The SAA7500 decoder outputs the audio data, of the selected stereo or mono channel,

as linear quantized 16-bit audio samples.

Selection of the desired audio channel, as well as stereo or mono mode, is controlled by inputs PA, PB, PC and PD.

These inputs may be driven directly by switches or controlled by a microcomputer.

When under the control of a microcomputer, the SAA7500 transmits serial data to the microcomputer on the type of

programme (16 stereo or 32 mono). The corresponding synchronization of the subframe is partly performed by the

SAA7500 (every 2 ms) and at a higher level by the microcomputer (every 16 ms). The SAA7500 also sends to the

microcomputer, programme information code data together with its clock and window signal.

The circuit automatically performs the system error correction and concealment. In the transmit error rate range of 0 to

3 × 10-3 a theoretical C/N (carrier-to-noise ratio) gain of about 6 dB is obtained. The residual error rate is nearly zero for

transmit error rates ≤ 3 × 10-4.

The remaining functions, such as clock recovery, main and subframe synchronization and scale factor decoding, are

protected in a similar manner so that they will not influence the residual error rate.

Clock recovery

The baseband signals A’ and B’ are connected to the SWA and SWB inputs of the SAA7500. For clock recovery, the

phase of the incoming data streams is compared with T10N (half the oscillator frequency). The output of the phase

comparator (PHD) controls, by means of the loop filter, the voltage controlled oscillator (both are external to the IC) and

thus its output signal T20N.

For energy dispersal, for example, in modulation pauses or with constant signals, the data streams are scrambled during

generation. The exceptions are the synchronization words and the special service bits. In order that the phase

correspondence between the recovered system clock (T10N) and the input signals A’ and B’ can be adjusted to a

minimum bit error rate (BER), a programmable phase shifter is provided (inputs LZA, LZB, LZC and ST3).

The differential decoder logic delivers the original data streams which may be exchanged depending on the number of

mixer stages on the transmission channel. The polarity of the two synchronization words will indicate if this is necessary,

if so the two data streams will be automatically switched over.

Synchronization

Using the synchronization circuit, the incoming data streams are first searched for 11-bit Barker codewords.

The synchronization circuit permits two errors for both synchronization words, which guards against failure of the

synchronization word. If the synchronization word has been detected, the following data is examined at frame length

intervals to see if the synchronization word is repeated. If it is repeated, it is acknowledged as a synchronization word

(window check) and an internal frame pulse generator takes over further control. There is also synchronization word

failure control which initiates a renewed synchronization word search and mutes the AF output if four successive

synchronization word failures occur.

To enhance the performance the result from the error correction circuit is used as an additional input to the

synchronization circuit. This is to avoid extra errors through synchronization loss in the case of relative high, but for

reception acceptable, bit error rates. This will not affect the rapid detection of a very high bit error rate or the

non-synchronization of the data stream. The decoder will function correctly with a bit error rate up to 3 × 10-3.

September 1989

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