X24C16P 데이터 시트보기 (PDF) - Xicor -> Intersil
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X24C16P Datasheet PDF : 15 Pages
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X24C16
Sequential Read
Sequential reads can be initiated as either a current
address read or random access read. The first word is
transmitted as with the other read modes, however, the
master now responds with an acknowledge, indicating it
requires additional data. The X24C16 continues to out-
put data for each acknowledge received. The read
operation is terminated by the master; by not responding
with an acknowledge and by issuing a stop condition.
Figure 9. Sequential Read
The data output is sequential, with the data from address
n followed by the data from n + 1. The address counter
for read operations increments all address bits, allowing
the entire memory contents to be serially read during
one operation. At the end of the address space (address
2047), the counter “rolls over” to 0 and the X24C16
continues to output data for each acknowledge re-
ceived. Refer to Figure 9 for the address, acknowledge
and data transfer sequence.
SLAVE
BUS ACTIVITY: ADDRESS
MASTER
SDA LINE
A
BUS ACTIVITY:
C
X24C16
K
DATA n
A
A
A
C
C
C
K
K
K
DATA n+1
DATA n+2
Figure 10. Typical System Configuration
S
T
O
P
P
DATA n+x
3840 FHD F15
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
VCC
PULL-UP
RESISTORS
3840 FHD F16
8
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