W48S87(1999) 데이터 시트보기 (PDF) - Cypress Semiconductor
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W48S87 Datasheet PDF : 21 Pages
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PRELIMINARY
W48S87-04
3.3V AC Electrical Characteristics (CPU3.3#_2.5 Input = 0) (continued)
IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
f
tR
tF
tD
fST
Zo
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Frequency Stabilization
from Power-up (cold start)
AC Output Impedance
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Average value during switching transition.
Used for determining series termination value.
CPU = 60/66.8 MHz
Min. Typ. Max.
14.31818
1
4
1
4
45
55
1.5
8
12
15
Unit
MHz
V/ns
V/ns
%
ms
Ω
REF0 Clock Output (Lump Capacitance Test Load = 45 pF)
Parameter
Description
Test Condition/Comments
f
Frequency, Actual
Frequency generated by crystal oscillator
tR
Output Rise Edge Rate Measured from 0.4V to 2.4V
tF
Output Fall Edge Rate Measured from 2.4V to 0.4V
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
fST
Frequency Stabilization Assumes full supply voltage reached within
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance Average value during switching transition.
Used for determining series termination value.
CPU = 60/66.8 MHz
Min. Typ. Max.
14.31818
1
4
1
4
40
60
1.5
17
20
25
Unit
MHz
V/ns
V/ns
%
ms
Ω
REF1 Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
f
Frequency, Actual
tR
Output Rise Edge Rate
tF
Output Fall Edge Rate
tD
Duty Cycle
fST
Frequency Stabilization
from Power-up (cold start)
Zo
AC Output Impedance
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Average value during switching transition.
Used for determining series termination value.
CPU = 60/66.8 MHz
Min. Typ. Max.
14.31818
1
4
1
4
40
55
1.5
20
25
35
Unit
MHz
V/ns
V/ns
%
ms
Ω
18
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