5962F0153501QXA 데이터 시트보기 (PDF) - Aeroflex UTMC
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5962F0153501QXA Datasheet PDF : 13 Pages
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Standard Products
UT54LVDS218 Deserializer
Data Sheet
October 2002
FEATURES
q 15 to 50MHz shift clock support
q 50% duty cycle on receiver output clock
q Low power consumption
q Cold sparing all pins
q +1V common mode range (around +1.2V)
q Narrow bus reduces cable size and cost
q Up to 1.05 Gbps throughput
q Up to 132 Megabytes/sec bandwidth
q 325 mV (typ) swing LVDS devices for low EMI
q PLL requires no external components
q Rising edge strobe
q Radiation-hardened design; total dose irradiation testing to
MIL-STD-883 Method 1019
- Total-dose: 300 krad(Si) and 1 Mrad(Si)
- Latchup immune (LET > 100 MeV-cm2/mg)
q Packaging options:
- 48-lead flatpack
q Standard Microcircuit Drawing 5962-01535
- QML Q and V compliant part
q Compatible with TIA/EIA-644 LVDS standard
INTRODUCTION
The UT54LVDS218 Deserializer converts the three LVDS data
streams back into 21 bits of CMOS/TTL data. At a transmit clock
frequency of 50MHz, 21 bits of TTL data are transmitted at a
rate of 350 Mbps per LVDS data channel. Using a 50 MHz clock,
the data throughput is 1.05 Gbit/s (132 Mbytes/sec).
The UT54LVDS218 Deserializer allows the use of wide, high
speed TTL interfaces while reducing overall EMI and cable size.
All pins have Cold Spare buffers. These buffers will be high
impedance when VDD is tied to VSS.
DATA (LVDS)
21
CMOS/TTL OUTPUTS
CLOCK (LVDS)
PLL
RECEIVER CLOCK OUT
POWER DOWN
Figure 1. UT54LVDS218 Deserializer Block Diagram
1
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