WM8804 데이터 시트보기 (PDF) - Wolfson Microelectronics plc

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WM8804

1:1 Digital Interface Transceiver with PLL

Wolfson Microelectronics plc 

Production Data

MASTER CLOCK TIMING

MCLK

tMCLKL

tMCLKH

tMCLKY

WM8804

Figure 1 Slave Mode MCLK Timing Requirements

Test Conditions

PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless stated.

PARAMETER

SYMBOL

System Clock Timing Information – Slave Mode

MCLK System clock cycle time

tMCLKY

MCLK System clock pulse width high

tMCLKH

MCLK System clock pulse width low

tMLCKL

MCLK Duty cycle

TEST CONDITIONS

MIN

27

11

11

40:60

TYP

MAX

60:40

Table 1 Master Clock Timing Requirements

UNIT

ns

ns

ns

%

DIGITAL AUDIO INTERFACE – MASTER MODE

BCLK

LRCLK

DOUT

tDL

tDDA

DIN

tDST

tDHT

Figure 2 Digital Audio Data Timing – Master Mode

Test Conditions

PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless stated.

PARAMETER

SYMBOL

Audio Data Input Timing Information

LRCLK propagation delay from

tDL

BCLK falling edge

DOUT propagation delay from

tDDA

BCLK falling edge

DIN setup time to BCLK rising

tDST

edge

DIN hold time from BCLK rising

tDHT

edge

TEST CONDITIONS

MIN

TYP

MAX

0

10

0

10

10

10

Table 2 Digital Audio Data Timing – Master Mode

UNIT

ns

ns

ns

ns

w

PD Rev 4.1 September 2007

7

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