WM8569 데이터 시트보기 (PDF) - Wolfson Microelectronics plc

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WM8569

24-bit, 192kHz Stereo CODEC with Volume Control

Wolfson Microelectronics plc 

WM8569

MASTER CLOCK TIMING

MCLK

t MCLKL

tMCLKH

t MCLKY

Production Data

Figure 1 ADC and DAC Master Clock Timing Requirements

Test Conditions

AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, DACMCLK and

ADCMCLK = 256fs unless otherwise stated.

PARAMETER

SYMBOL

System Clock Timing Information

MCLK System clock pulse width

high

tMCLKH

MCLK System clock pulse width

low

tMCLKL

MCLK System clock cycle time

tMCLKY

MCLK Duty cycle

Table 1 Master Clock Timing Requirements

TEST CONDITIONS

MIN

11

11

28

40:60

TYP

MAX

UNIT

ns

ns

ns

60:40

DIGITAL AUDIO INTERFACE – MASTER MODE

Figure 2 Audio Interface – Master Mode

w

PD Rev 4.0 June 2006

8

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