WM8776 데이터 시트보기 (PDF) - Wolfson Microelectronics plc
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WM8776 Datasheet PDF : 57 Pages
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Production Data
DIGITAL AUDIO INTERFACE – SLAVE MODE
DACBCLK
ADCBCLK
WM8776 ADCLRC
CODEC DACLRC
DOUT
DIN
DVD
Controller
WM8776
Figure 4 Audio Interface – Slave Mode
ADCBCLK/
DACBCLK
DACLRC/
ADCLRC
DIN
DOUT
tBCH
tBCL
tBCY
tDS
tDD
tLRH
tDH
tLRSU
Figure 5 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, ADC/DACMCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
ADC/DACBCLK cycle time
tBCY
ADC/DACBCLK pulse width
tBCH
high
ADC/DACBCLK pulse width
tBCL
low
DACLRC/ADCLRC set-up
time to ADC/DACBCLK
rising edge
tLRSU
DACLRC/ADCLRC hold
tLRH
time from ADC/DACBCLK
rising edge
DIN set-up time to
tDS
DACBCLK rising edge
DIN hold time from
tDH
DACBCLK rising edge
DOUT propagation delay
tDD
from ADCBCLK falling edge
TEST CONDITIONS
MIN
TYP
MAX
50
20
20
10
10
10
10
0
10
Table 3 Digital Audio Data Timing – Slave Mode
Note: ADCLRC and DACLRC should be synchronous with MCLK, although the WM8776 interface is tolerant of phase
variations or jitter on these signals.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
w
PD Rev 4.0 April 2005
11
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