WM8771IFT 데이터 시트보기 (PDF) - Wolfson Microelectronics plc

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WM8771IFT

24-bit, 192kHz 8-Channel Codec

Wolfson Microelectronics plc 

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DEVICE DESCRIPTION

WM8771

INTRODUCTION

WM8771 is a complete 8-channel DAC, 2-channel ADC audio codec, including digital interpolation

and decimation filters, multi-bit sigma delta stereo ADC, and switched capacitor multi-bit sigma delta

DACs with digital volume controls on each channel and output smoothing filters.

The device is implemented as four separate stereo DACs and a stereo ADC with flexible input

multiplexor, in a single package and controlled by a single interface.

The four stereo channels may either be used to implement a 5.1 channel surround system, with

additional stereo channel for a stereo mix down channel, or for a complete 7.1 channel surround

system.

Each stereo DAC has its own data input DIN1/2/3/4. DAC word clock DACLRC is shared between

them. The stereo ADC has it’s own data output DOUT, and word clock ADCLRC. BITCLK and MCLK

are shared between the ADCs and DACs. The Audio Interface may be configured to operate in either

master or slave mode. In Slave mode ADCLRC, DACLRC and BCLK are all inputs. In Master mode

ADCLRC, DACLRC and BCLK are all outputs.

The input multiplexor to the ADC is configured to allow large signal levels to be input to the ADC,

using external resistors to reduce the amplitude of larger signals to within the normal operating range

of the ADC. The ADC input PGA also allows input signals to be gained up to +19dB and attenuated

down to -12dB. This allows the user maximum flexibility in the use of the ADC.

Three individually selectable stereo record outputs are also provided on REC1/2/3. It is intended that

the REC1/2/3 outputs are only used to drive high impedance buffers.

Each DAC has its own digital volume control. In addition a zero cross detect circuit is provided for

each DAC. The digital volume control detects a transition through the zero point before updating the

volume. This minimises audible clicks and ‘zipper’ noise as the gain values change.

Control of internal functionality of the device is by 3-wire serial control interface. An SPI or CCB type

interface may used, selectable by the state of the CE pin on the rising edge of RESETB. The control

interface may be asynchronous to the audio data interface as control data will be re-synchronised to

the audio processing internally.

Operation using system clock of 128fs, 192fs, 256fs, 384fs, 512fs or 768fs is provided. In Slave

mode selection between clock rates is automatically controlled. In master mode the master clock to

sample rate ratio is set by control bits ADCRATE and DACRATE. ADC and DAC may run at different

rates within the constraint of a common master clock for the ADC and DACs. For example with

master clock at 24.576MHz, a DAC sample rate of 96kHz (256fs mode) and an ADC sample rate of

48kHz (512fs mode) can be accommodated. Master clock sample rates (fs) from less than 8ks/s up

to 192ks/s are allowed, provided the appropriate system clock is input.

The audio data interface supports right, left and I2S interface formats along with a highly flexible DSP

serial port interface.

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PP Rev 2.0 December 2001

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