W921E880A/W921C880
6.2.2 Stack Reg. Area
There are 8 bit stack pointers in this chip located at addresses 040H − 0FFH. After a power on reset
the stack pointer will be set to 0FFH. The stack pointer will be decreased by 4 each time a CALLP or
interrupt occurs, and will be increased by 4 each time the RTN or RTNI instruction is executed. The
format of the stack pointer is shown in the following table.
0F8H
Z
C
PC12
0F9H PC11 PC10 PC9 PC8
0FAH
PC7
PC6
PC5
PC4
0FBH
PC3
PC2
PC1
PC0
0FCH
Z
C
PC12
0FDH PC11 PC10 PC9 PC8
0FEH
PC7
PC6
PC5
PC4
0FFH
PC3 PC2 PC1 PC0
STACK 1
STACK 0
6.2.3 Working Reg. Area
The area located from 040H to 04FH is known as the Working Reg. The instruction MOV WRn, A or
MOV A, WRn can move the A reg. data to the Working reg. or move the Working reg. data to the A
reg. directly within 1 word/1 machine cycle. Unlike other direct instructions such as MOV Mx, A or
MOV A, Mx, these instructions use 2 words/2 machine cycles. Therefore, the Working reg. can
reduce the ROM program memory size and improve the control speed of the application circuit.
For arithmetic and logic operations only WR0−WR7 are available, that is only 040H to 047H can be
active.
The instructions are as follow:
ADD A,
ADC A,
SUB A,
SBC A,
ANL A,
ORL A,
XRL A,
CMP A,
where x = 0 -- 7.
WRx
WRx
WRx
WRx
WRx
WRx
WRx
WRx
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