W83195BR-341 데이터 시트보기 (PDF) - Winbond

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W83195BR-341

WINBOND CLOCK GENERATOR FOR VIA P4/KT SERIES CHIPSET

Winbond 

W83195BR-341/W83195BG-341

CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET

7.7 Register 7: M/N Program (Default: 2Fh)

BIT

NAME PWD

FUNCTION DESCRIPTION

7 N_DIV [7] 0

6 N_DIV [6] 0

5 N_DIV [5] 1

Programmable N divisor value bit 7 ~0.

4 N_DIV [4] 0

The bit 8 is defined in Register 6, Bit 7.

3 N_DIV [3] 1

The bit 9 is defined in Register 9, Bit 7.

2 N_DIV [2] 1

1 N_DIV [1] 1

0 N_DIV [0] 1

7.8 Register 8: Spread Spectrum Program (Default: 1Fh)

BIT

NAME

PWD

FUNCTION DESCRIPTION

7 SP_UP [3]

0 Spread Spectrum Up Counter bit 3 ~ bit 0.

6 SP_UP [2]

0

5 SP_UP [1]

0

4 SP_UP [0]

1

3 SP_DOWN [3] 1 Spread Spectrum Down Counter bit 3 ~ bit 0

2 SP_DOWN [2]

1 SP_DOWN [1]

1 2’s complement representation.

1 Ex: 1 -> 1111; 2 -> 1110; 7 -> 1001; 8 -> 1000

0 SP_DOWN [0] 1

7.9 Register 9: Divider Ratio (Default: 03h)

BIT

NAME

PWD

FUNCTION DESCRIPTION

7

N<9>

0 Programmable N divisor value bit 9

6 SEL_CLKSTOP 0 Refer to Table-2

5 Reserved

0 Reserved

4 Reserved

0 Reserved

3 Reserved

0 Reserved

2

DS2

1

DS1

0 Define the CPU/AGP/PCI divider ratio

1 Refer to Table-3

0

DS0

1

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