W78E58
XTAL1
TCH
TCL
F OP, TCP
PARAMETER
Operating Speed
Clock Period
Clock High
Clock Low
SYMBOL
FOP
TCP
TCH
TCL
MIN.
0
25
10
10
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
TYP.
-
-
-
-
MAX.
40
-
-
-
UNIT
MHz
nS
nS
nS
NOTES
1
2
3
3
Program Fetch Cycle
PARAMETER
Address Valid to ALE Low
Address Hold from ALE Low
ALE Low to PSEN Low
PSEN Low to Data Valid
Data Hold after PSEN High
Data Float after PSEN High
ALE Pulse Width
PSEN Pulse Width
SYMBOL
TAAS
TAAH
TAPL
TPDA
TPDH
TPDZ
TALW
TPSW
MIN.
1 TCP -∆
1 TCP -∆
1 TCP -∆
-
0
0
2 TCP -∆
3 TCP -∆
TYP.
-
-
-
-
-
-
2 TCP
3 TCP
MAX.
-
-
-
2 TCP
1 TCP
1 TCP
-
-
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
NOTES
4
1, 4
4
2
3
4
4
Notes:
1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "∆" (due to buffer driving delay and wire loading) is 20 nS.
Data Read Cycle
PARAMETER
ALE Low to RD Low
RD Low to Data Valid
SYMBOL MIN. TYP.
TDAR
3 TCP -∆
-
TDDA
-
-
MAX.
3 TCP +∆
4 TCP
UNIT
nS
nS
NOTE
S
1, 2
1
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