W158 데이터 시트보기 (PDF) - SpectraLinear Inc

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W158

Spread Spectrum System Frequency Synthesizer

SpectraLinear Inc 

Timing Diagrams (continued)

PCI_STOP# Timing Diagram[18, 22, 23, 24, 25, 26]

CPU

PCI

(internal)

PCI_STOP#

CPU_STOP#

HI

PWRDWN#

HI

PCI_F

(external)

PCI

(external)

PWRDWN# Timing Diagram[18, 22, 23, 27, 28]

CPU

(internal)

PCI

(internal)

PWRDWN#

CPU

(external)

PCI

(external)

VCO

Crystal

Notes:

23. All internal timing is referenced to the CPU clock.

24. PCI_STOP# signal is an input signal that must be made synchronous to PCI_F output.

25. All other clocks continue to run undisturbed.

26. PWRDWN# and CPU_STOP# are shown in a HIGH state.

27. PWRDWN is an asynchronous input and metastable conditions could exist. This signal must be synchronized.

28. The shaded Sections on the VCO and the Crystal signals indicate an active clock.

W158

Rev 1.0, November 21, 2006

Page 6 of 12

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