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W137H 데이터 시트보기 (PDF) - Cypress Semiconductor

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W137H
Cypress
Cypress Semiconductor Cypress
W137H Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
W137
48-MHz and 24-MHz Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter
Description
f
Frequency, Actual
Test Condition/Comments
Determined by PLL divider ratio (see n/m below)
fD
Deviation from 48 MHz
(48.008 48)/48
m/n
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
tR
Output Rise Edge Rate Measured from 0.4V to 2.4V
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
fST
Frequency Stabilization Assumes full supply voltage reached within 1 ms
from Power-up (cold start) from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
CPU = 66.6/100 MHz
Min. Typ. Max.
48.008
24.004
+167
57/17, 57/34
0.5
2
0.5
2
45
55
3
25
Unit
MHz
ppm
V/ns
V/ns
%
ms
Ordering Information
Ordering Code
Package
Name
W137
H
X
Package Type
28-pin SSOP (209 mils)
28-pin TSSOP (173 mils)
Intel is a registered trademark of Intel Corporation.
Document #: 38-00821
8

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