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VS1053B

Ogg Vorbis/MP3/AAC/WMA/MIDI AUDIO CODEC

Unspecified 

VS1053b preliminary

VS1053B

VS1053b -

Ogg Vorbis/MP3/AAC/WMA/MIDI

AUDIO CODEC

Features

Description

• Decodes Ogg Vorbis;

MPEG 1 & 2 audio layer III (CBR +VBR

+ABR); layers I & II optional;

MPEG4 / 2 AAC-LC(+PNS),

HE-AAC v2 (Level 3) (SBR + PS);

WMA 4.0/4.1/7/8/9 all profiles (5-384 kbps);

WAV (PCM + IMA ADPCM);

General MIDI 1 / SP-MIDI format 0 files

• Encodes Ogg Vorbis with software plu-

gin (available Q4/2007)

VS1053b is a single-chip Ogg Vorbis/MP3/AAC/-

WMA/MIDI audio decoder and an IMA ADPCM

and user-loadable Ogg Vorbis encoder. It contains

a high-performance, proprietary low-power DSP

processor core VS DSP4, working data memory,

16 KiB instruction RAM and 0.5+ KiB data RAM

for user applications running simultaneously with

any built-in decoder, serial control and input data

interfaces, upto 8 general purpose I/O pins, an

UART, as well as a high-quality variable-sample-

• Encodes IMA ADPCM from mic/line (stereo)

• Streaming support for MP3 and WAV

• EarSpeaker Spatial Processing

rate stereo ADC (mic, line, line + mic or 2×line)

and stereo DAC, followed by an earphone ampli-

fier and a common voltage buffer.

• Bass and treble controls

• Operates with a single 12..13 MHz clock

• Can also be used with a 24..26 MHz clock

VS1053b receives its input bitstream through a

serial input bus, which it listens to as a system

slave. The input stream is decoded and passed

• Internal PLL clock multiplier

• Low-power operation

• High-quality on-chip stereo DAC with no

phase error between channels

• Zero-cross detection for smooth volume

change

through a digital volume control to an 18-bit over-

sampling, multi-bit, sigma-delta DAC. The decod-

ing is controlled via a serial control bus. In addi-

tion to the basic decoding, it is possible to add

application specific features, like DSP effects, to

the user RAM memory.

• Stereo earphone driver capable of driving a

30 Ω load

• Quiet power-on and power-off

Optional factory-programmable unique chip ID pro-

vides basis for digital rights management or unit

identification features.

• I2S interface for external DAC

I2S

• Separate voltages for analog, digital, I/O

• On-chip RAM for user code and data differential

mic / line 1

VS1053

MIC AMP

MUX

Stereo

ADC

Stereo

DAC

• Serial control and data interfaces

line 2

GPIO

8

Stereo Ear−

phone Driver

audio

L

R

output

• Can be used as a slave co-processor

GPIO

X ROM

• SPI flash boot for special applications

DREQ

SO

• UART for debugging purposes

SI

SCLK

• New functions may be added with software XCS

Serial

Data/

Control

Interface

VSDSP4

X RAM

and upto 8 GPIO pins

XDCS

Y ROM

• Lead-free RoHS-compliant package (Green) RX

TX

UART

Y RAM

Clock

multiplier

Instruction

RAM

Instruction

ROM

Version 0.5, 2007-12-03

1

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