UPD72862 데이터 시트보기 (PDF) - NEC => Renesas Technology

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UPD72862

IEEE1394 OHCI HOST CONTROLLER

NEC => Renesas Technology 

µPD72862

2.1.11 Offset_10 Base Address 0 Register

This register specifies the base memory address for accessing all the “Operation registers” (i.e. control,

configuration, and status registers) of the µPD72862, while the BIOS is expected to set this value during power-up

reset.

Bits

11-0

31-12

R/W

Description

R

Constant value of 000H. These bits are “read-only”.

R/W

-

2.1.12 Offset_2C Subsystem Vendor ID Register

This register identifies the subsystem that contains the NEC’s µPD72862 function. While the ID is assigned by the

PCI_SIG committee, the value should be loaded into the register from the external serial EEPROM after power-up

reset. Access to this register through PCI-bus is prohibited.

Bits

15-0

R/W

R

Default value of 1033H.

Description

2.1.13 Offset_2E Subsystem ID Register

This register identifies the type of the subsystem that contains the NEC’s µPD72862 function. While the ID is

assigned by the manufacturer, the value should be loaded into the register from the external serial EEPROM after

power-up reset. Access to this register through PCI-bus is prohibited.

Bits

15-0

R/W

R

Default value of 0063H.

Description

2.1.14 Offset_30 Expansion Rom Base Address Register

This register is not supported by the current implementation of the µPD72862.

Bits

31-0

R/W

R

Reserved Constant value of 0.

Description

2.1.15 Offset_34 Cap_Ptr Register

This register points to a linked list of additional capabilities specific to the µPD72862, the NEC’s implementation of

the 1394 OpenHCI specification.

Bits

7-0

R/W

Description

R

Constant value of 60H. The value represents an offset into the µPD72862’s PCI Configuration

Space for the location of the first item in the New Capabilities Linked List.

Data Sheet S14265EJ2V0DS00

15

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