UPD72873 데이터 시트보기 (PDF) - NEC => Renesas Technology
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UPD72873 Datasheet PDF : 40 Pages
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µPD72873
3.1.11 Offset_10 Base Address 0 Register
This register specifies the base memory address for accessing all the “Operation registers” (i.e. control,
configuration, and status registers) of the µPD72873, while the BIOS is expected to set this value during power-up
reset.
Bits
11-0
31-12
R/W
Description
R
Constant value of 000H. These bits are “read-only”.
R/W
-
3.1.12 Offset_2C Subsystem Vendor ID Register
This register identifies the subsystem that contains the NEC’s µPD72873 function. While the ID is assigned by the
PCI_SIG committee, the value should be loaded into the register from the external serial ROM after power-up reset.
Access to this register through PCI-bus is prohibited.
Bits
15-0
R/W
R
Default value of 1033H.
Description
3.1.13 Offset_2E Subsystem ID Register
This register identifies the type of the subsystem that contains the NEC’s µPD72873 function. While the ID is
assigned by the manufacturer, the value should be loaded into the register from the external serial EEPROM after
power-up reset. Access to this register through PCI-bus is prohibited.
Bits
15-0
R/W
R
Default value of 00E7H.
Description
3.1.14 Offset_34 Cap_Ptr Register
This register points to a linked list of additional capabilities specific to the µPD72873, the NEC’s implementation of
the 1394 OHCI specification.
Bits
7-0
R/W
Description
R
Constant value of 60H. The value represents an offset into the µPD72873’s PCI Configuration
Space for the location of the first item in the New Capabilities Linked List.
3.1.15 Offset_3C Interrupt Line Register
This register provides the interrupt line routing information specific to the µPD72873, the NEC’s implementation of
the 1394 OHCI specification.
Bits
7-0
R/W
Description
R/W
Default value of 00H. It specifies which input of the host system interrupt controller the
interrupt pin of the µPD72873 is connected to.
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Preliminary Data Sheet S15305EJ2V0DS
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