UPD72001C-11 데이터 시트보기 (PDF) - NEC => Renesas Technology
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UPD72001C-11 Datasheet PDF : 40 Pages
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µPD72001-11, 72001-A8
Serial control:
Parameter
Symbol
Condition
Transmit/receive data cycle
tCYD
STRXC, TRXC input clock cycle
tCYC
STRXC, TRXC input
clock pulse width
High
Low
tWCH
tWCL
STRXC, TRXC ↓ → TXD delay time
TRXC ↓ → TXD delay time
RXD setup time (vs. STRXC, TRXC ↑)
RXD hold time (vs. STRXC, TRXC ↑)
RXD → TXD delay time
TXD → INT delay time
TXD → DRQTX delay time
RXC ↑ Note → INT delay time
RXC ↑ Note → DRQRX delay time
RD ↓ → DRQRX ↓ delay time
WR ↓ → DRQTX ↓ delay time
tDTCTD1
tDTCTD2
tDTCTD3
tSRDRC
tHRCRD
tDRDTD1
tDRDTD2
tDTDIQ
tDTDDQ
tDRCIQ
tDRCDQ
tDRDQ
tDWDQ
TA = –10 to +70 °C
TA = –40 to +85 °C
×1 mode, COP, BOP
×16, 32, 64 mode
TRXC is output
When DPLL is not used
When DPLL is not used
ECHO BACK mode
Without SDLC Loop delay
TX INT mode
TX DMA mode
RX INT mode
RX DMA mode
Note Of STRXC and TRXC, the one used as the receive clock.
Rated Value
Unit
MIN. MAX.
5
tCYK
90
ns
40
ns
40
ns
45
100
ns
300
ns
0
100
ns
0
ns
120
ns
100
ns
100
ns
4
6
tCYK
4
6
tCYK
7
11
tCYK
7
11
tCYK
120
ns
120
ns
Interrupt control:
Parameter
Symbol
Condition
INTAK low-pulse width
INTAK high-pulse width
PRI → PRO delay time
INT ↓ → PRO ↑ delay time
2nd INTAK ↓ → INT ↑ delay time
tWIAL
tWIAH
tDPIPO
tDIQPO
tDIAIQ
SR2B read RD ↓ → INT ↑delay time tDRDIQ
PRI setup time (vs. INTAK ↓)
PRI hold time (vs. INTAK ↑)
PRI setup time (vs. INTAK ↓)
PRI hold time (vs. INTAK ↑)
INTAK → data output delay time
INTAK → data float delay time
tSPIIA1
tHIAPI1
tSPIIA2
tHIAPI2
tDIAD
tFIAD
INT output level = 0.8 VNote
INT output level = 2.2 VNote
INT output level = 0.8 VNote
INT output level = 2.2 VNote
When vector output is enabled
When vector output is disabled
Rated Value
Unit
MIN. MAX.
120
ns
120
ns
50
ns
–20
+50
ns
120
ns
300
ns
150
ns
300
ns
0
ns
20
ns
20
ns
20
ns
120
ns
10
85
ns
Note Measured value with 2-kΩ pull-up resistor and 100-pF load capacitance connected
17
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