UPD6345C 데이터 시트보기 (PDF) - NEC => Renesas Technology

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UPD6345C

8 BIT SERIAL IN/PARALLEL OUT DRIVER

NEC => Renesas Technology 

PIN CONFIGURATION (Top View)

VSS 1

EN 2

LAT 3

SO 4

O8 5

O7 6

O6 7

O5 8

16 VDD

15 RES

14 SCK

13 SIN

12 O1

11 O2

10 O3

9 O4

µPD6345

PIN IDENTIFICATION

Pin No.

1

2

3

4

5 to 12

13

14

15

16

Symbol

GND

EN

LAT

SO

O8 to O1

SIN

SCK

RES

VDD

Pin name

Input/Output

Function

Ground

—

Connection to Ground (GND) of system.

Output Enable

Input

When this pin is low or open, all outputs are OFF, and data is output

during high.

Latch Enable

Input

When this pin is low or open, data is latched and data is through to

output during high.

Serial data Output

Output

Serial data is output on positive-going transition of the clock.

In case of connection to cascade additional device (µPD6345), this

pin will be connected to SIN terminal of additional device.

Driver Output

Output

High Voltage and Current Driver Outputs.

Serial data Input

Input

Data is loaded to shift register on positive-going transition.

Clock

Input

Data of SIN is loaded to shift register on positive-going transition of

SCK. Also, serial data is output from SO on positive-going transition

of SCK.

Reset

Input

When this pin is low or open, data of shift register is all cleared, and

this device operate normally during high.

Power Supply

—

Normally supply 5 V.

2

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