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UPD161660 데이터 시트보기 (PDF) - NEC => Renesas Technology

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UPD161660
NEC
NEC => Renesas Technology NEC
UPD161660 Datasheet PDF : 15 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
2. PIN CONFIGURATION (Pad Layout)
Chip size: X = 4.20 mm, Y = 4.35 mm
Pad size : 100 x 100 µm2
(1) Alignment mark
30 µm
30 µm
30 µm
30 µm 30 µm 30 µm
(2) Arrangement
µPD161660
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
DUMMY 17
VDD2 16
VDD1 15
MVT 14
VT 13
VREF 12
MVS 11
VS 10
DUMMY 9
DUMMY 8
VDC 7
DUMMY 6
DUMMY 5
VCE 4
VCD2 3
VCD12 2
DUMMY 1
Chip Surface
(Bump Side)
Y
X
35 DUMMY
36 TESTIN1
37 TESTIN2
38 TESTIN3
39 DUMMY
40 VSS
41 DUMMY
42 VCC1
43 DUMMY
44 DUMMY
45 TESTIN4
46 TESTIN5
47 TESTOUT
48 TESTIN6
49 DVSS
50 LACS0
51 DUMMY
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
Alignment Mark
(No Bump)
X = 4.20 mm
Alignment Mark
(No Bump)
Data Sheet S14799E1V0DS
3

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